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Issue No.01 - January (2009 vol.58)
pp: 132-138
Dimitris Nikolos , University of Patras, Patras
Dimitrios Kagaris , Southern Illinois University, Carbondale
Samara Sudireddy , Southern Illinois University, Carbondale
Spyros Gidaros , University of Patras, Patras
ABSTRACT
In this paper we present a new search method for test set embedding using an accumulator driven with an additive constant C. We formulate the problem of finding the location of a test pattern in the generated sequence in terms of a linear Diophantine equation with two variables, which is known to be solved quickly in linear time. We show that only one Diophantine equation needs to be solved per test set irrespective of its size. Next we show how to find the starting state, for a given constant C and test set T, such that the generated sequence can reproduce T with minimum length. Finally, we show that the best constant Copt (in terms of shortest test length) for the embedding of T using an accumulator of size n can be found in O(2n+F|T|) steps, instead of O(n(2^n)|T|) steps of a previous approach, where F depends on the particular test set and can be significantly smaller than its worst case value of 2^(n-2). The value of F can also be further reduced while providing a guaranteed approximation bound of the shortest test length. Experimental results show the computational improvements.
INDEX TERMS
Built-in self test, Reliability and Testing, Integrated Circuits, Hardware, Test set embedding, accumulator-based test pattern generation
CITATION
Dimitris Nikolos, Dimitrios Kagaris, Samara Sudireddy, Spyros Gidaros, "An Improved Search Method for Accumulator-Based Test Set Embedding", IEEE Transactions on Computers, vol.58, no. 1, pp. 132-138, January 2009, doi:10.1109/TC.2008.182
REFERENCES
[1] N. Jha and S. Gupta, Testing of Digital Systems. Cambridge Univ. Press, 2003.
[2] M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design. Computer Science Press, 1990.
[3] P.H. Bardell, W.H. McAnney, and J. Savir, Built-In Test for VLSI: Pseudo-Random Techniques. John Wiley & Sons, 1987.
[4] J. Rajski and J. Tyszer, Arithmetic Built-In Self-Test for Embedded Systems. Prentice Hall PTR, 1998.
[5] S. Gupta, J. Rajski, and J. Tyszer, “Test Pattern Generation Based on Arithmetic Operations,” Proc. IEEE Int'l Conf. Computer-Aided Design (ICCAD '94), pp. 117-124, 1994.
[6] A. Gupta, J. Rajski, and J. Tyszer, “Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns,” IEEE Trans. Computers, vol. 45, no. 8, pp.939-949, Aug. 1996.
[7] A. Stroele, “Arithmetic Pattern Generators for Built-In Self-Test,” Proc. Int'l Conf. Computer Design (ICCD '96), pp. 131-134, 1996.
[8] A. Stroele, “BIST Pattern Generators Using Addition and Subtraction Operations,” J. Electronic Testing: Theory and Applications, vol. 11, pp. 69-80, 1997.
[9] A. Stroele and F. Mayer, “Methods to Reduce Test Application Time for Accumulator-Based Self Test,” Proc. 15th IEEE VLSI Test Symp. (VTS '97), pp. 48-53, 1997.
[10] A. Stroele, “Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions,” Proc. 16th IEEE VLSI Test Symp. (VTS '98), pp. 78-85, 1998.
[11] R. Dorsch and H. Wunderlich, “Accumulator-Based Deterministic BIST,” Proc. Int'l Test Conf. (ITC '98), pp. 412-421, 1998.
[12] S. Chiusano, P. Prinetto, and H.J. Wunderlich, “Nonintrusive BIST for Systems-on-a-Chip,” Proc. Int'l Test Conf. (ITC '00), pp. 644-651, 2000.
[13] S. Cataldo, S. Chiusano, P. Prinetto, and H.J. Wunderlich, “Optimal Hardware Pattern Generation for Functional BIST,” Proc. Design, Automation and Test in Europe Conf. (DATE '00), pp. 292-297, 2000.
[14] S. Chiusano, S. Di Carlo, P. Prinetto, and H.J. Wunderlich, “On Applying the Set Covering Model to Reseeding,” Proc. Design, Automation and Test in Europe Conf. (DATE '01), pp. 156-160, 2001.
[15] E. Kalligeros, X. Kavousianos, D. Bakalis, and D. Nikolos, “On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST,” J.Electronic Testing: Theory and Applications, vol. 18, pp. 315-332, 2002.
[16] G. Dimitrakopoulos, D. Nikolos, and D. Bakalis, “Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register,” Proc. 12th IEEE Int'l On-Line Testing Symp. (IOLTS '02), pp. 152-157, 2002.
[17] S. Manich, L. Garcia, L. Balado, E. Lupon, J. Rius, R. Rodriguez, and J. Figueras, “On the Selection of Efficient Arithmetic Additive Test Pattern Generators,” Proc. IEEE European Test Workshop, pp. 9-14, 2003.
[18] I. Voyiatzis, “Test Vector Embedding into Accumulator-Generated Sequences: A Linear-Time Solution,” IEEE Trans. Computers, vol. 54, no. 4, pp. 476-484, Apr. 2005.
[19] D. Kagaris, P. Karpodinis, and D. Nikolos, “On Obtaining Maximum Length Sequences for Accumulator-Based Serial TPG,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 11, pp. 2578-2586, Nov. 2006.
[20] N. Mukherjee, M. Kassab, J. Rajski, and J. Tyszer, “Arithmetic Built-In Self Test for High-Level Synthesis,” Proc. 13th IEEE VLSI Test Symp. (VTS '95), pp. 132-139, 1995.
[21] A. Stroele, “Synthesis for Arithmetic Built-In Self-Test,” Proc. 18th IEEE VLSI Test Symp. (VTS '00), pp. 165-170, 2000.
[22] D. Berthelot, M.L. Flottes, and B. Rouzeyre, “BISTing Data Paths at Behavioral Level,” Proc. Int'l Test Conf. (ITC '00), pp. 672-680, 2000.
[23] A. Stroele and F. Mayer, “Test Scheduling with Loop Folding and Its Application to Test Configurations with Accumulators,” Proc. Eighth Asian Test Symp. (ATS '99), pp. 101-106, 1999.
[24] D. Berthelot, M.L. Flottes, and B. Rouzeyre, “OptiBIST: A Tool for BISTing Datapaths,” Proc. IEEE European Test Workshop, pp. 123-127, 1998.
[25] D. Berthelot, M.L. Flottes, and B. Rouzeyre, “BISTing Datapaths under Heterogeneous Test Schemes,” J. Electronic Testing: Theory and Applications, vol. 14, pp. 115-123, 1999.
[26] F. Mayer and A.P. Stroele, “A Versatile BIST Technique Combining Test Registers and Accumulators,” Proc. 13th Int'l Conf. VLSI Design (VLSI Design '00), pp. 412-415, 2000.
[27] J. Hunter, Number Theory. Oliver & Boyd, 1964.
[28] I. Hamzaoglu and J.H. Patel, “Test Set Compaction Algorithms for Combinational Circuits,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 8, pp. 957-963, Aug. 2000.
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