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Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
January 2009 (vol. 58 no. 1)
pp. 32-45
ASCII Text
x 
 
Brett Stanley Feero, Partha Pratim Pande, "Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation," IEEE Transactions on Computers, vol. 58, no. 1, pp. 32-45, January, 2009.
 
 
BibTex
x
 
@article{ 10.1109/TC.2008.142,
author = {Brett Stanley Feero and Partha Pratim Pande},
title = {Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation},
journal ={IEEE Transactions on Computers},
volume = {58},
number = {1},
issn = {0018-9340},
year = {2009},
pages = {32-45},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2008.142},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
IS - 1
SN - 0018-9340
SP32
EP45
EPD - 32-45
A1 - Brett Stanley Feero,
A1 - Partha Pratim Pande,
PY - 2009
KW - Integrated Circuits
KW - VLSI
KW - Performance Analysis and Design Aids
KW - Emerging technologies
KW - System architectures
KW - integration and modeling
KW - Interconnection architectures
KW - Multi-core/single-chip multiprocessors
KW - On-chip interconnection networks
VL - 58
JA - IEEE Transactions on Computers
ER -
 
Brett Stanley Feero, ARM Ltd., Cambridge
Partha Pratim Pande, Washington State University, Pullman
The Network-on-Chip (NoC) paradigm has emerged as a revolutionary methodology for integrating a very high number of intellectual property (IP) blocks in a single die. The achievable performance benefit arising out of adopting NoCs is constrained by the performance limitation imposed by the metal wire, which is the physical realization of communication channels. With technology scaling, only depending on the material innovation will extend the lifetime of conventional interconnect systems a few technology generations. According to International Technology Roadmap for Semiconductors (ITRS) for the longer term, new interconnect paradigms are in need. The conventional two dimensional (2D) integrated circuit (IC) has limited floor-planning choices, and consequently it limits the performance enhancements arising out of NoC architectures. Three dimensional (3D) ICs are capable of achieving better performance, functionality, and packaging density compared to more traditional planar ICs. On the other hand, NoC is an enabling solution for integrating large numbers of embedded cores in a single die. 3D NoC architectures combine the benefits of these two new domains to offer an unprecedented performance gain. In this paper we evaluate the performance of 3D NoC architectures and demonstrate their superior functionality in terms of throughput, latency, energy dissipation and wiring area overhead compared to traditional 2D implementations.

[1] L. Benini and G. De Micheli, “Networks on Chips: A New SoC Paradigm,” Computer, pp. 70-78, Jan. 2002.
[2] P. Magarshack and P.G. Paulin, “System-on-Chip beyond the Nanometer Wall,” Proc. 40th Design Automation Conf. (DAC '03), pp. 419-424, 2003.
[3] W.J. Dally and B. Towles, “Route Packets, Not Wires: On-Chip Interconnection Networks,” Proc. 38th Design Automation Conf. (DAC '01), pp. 683-689, June 2001.
[4] M.A. Horowitz et al., “The Future of Wires,” Proc. IEEE, vol. 89, no. 4, pp. 490-504, Apr. 2001.
[5] C. Grecu, P.P. Pande, A. Ivanov, and R. Saleh, “Timing Analysis of Network on Chip Architectures for MP-SoC Platforms,” Microelectronics J., vol. 36, no. 9, pp. 833-845, Sept. 2005.
[6] H.G. Lee et al., “On-Chip Communication Architecture Exploration: A Quantitative Evaluation of Point-to-Point, Bus, and Network-on-Chip Approaches,” ACM Trans. Design Automation of Electronic Systems, vol. 12, no. 3, pp. 1-20, Aug. 2007.
[7] A.W. Topol et al., “Three-Dimensional Integrated Circuits,” IBM J. Research and Development, vol. 50, nos. 4/5, July-Sept. 2006.
[8] W.R. Davis et al., “Demystifying 3D ICS: The Pros and Cons of Going Vertical,” IEEE Design and Test of Computers, vol. 22, no. 6, Nov./Dec. 2005.
[9] Y. Deng et al., “2.5D System Integration: A Design Driven System Implementation Schema,” Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), 2004.
[10] M. Ieong et al., “Three Dimensional CMOS Devices and Integrated Circuits,” Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2003.
[11] P. Jacob et al., “Predicting the Performance of a 3D Processor-Memory Stack,” IEEE Design and Test of Computers, vol. 22, no. 6, pp. 540-547, Nov./Dec. 2005.
[12] F. Li et al., “Design and Management of 3D Chip Multiprocessors Using Network-in-Memory,” Proc. 33rd Int'l Symp. Computer Architecture (ISCA '06), pp. 130-141, June 2005.
[13] C. Addo-Quaye, “Thermal-Aware Mapping and Placement for 3D NoC Designs,” Proc. IEEE Int'l System on Chip Conf. (SOCC '05), pp. 25-28, 2005.
[14] V.F. Pavlidis and E.G. Friedman, “3-D Topologies for Networks-on-Chip,” IEEE Trans. Very Large Scale Integration (VLSI '07), pp.1081-1090, Oct. 2007.
[15] S. Vangal et al., “An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS,” Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC'07), pp.98-99, 2007.
[16] R.I. Greenberg and L. Guan, “An Improved Analytical Model for Wormhole Routed Networks with Application to Butterfly Fat Trees,” Proc. Int'l Conf. Parallel Processing (ICPP '97), pp. 44-48, Aug. 1997.
[17] C. Grecu et al., “A Scalable Communication-Centric SoC Interconnect Architecture,” Proc. Fifth Int'l Symp. Quality Electronic Design (ISQED '04), pp. 343-348, 2004.
[18] P. Guerrier and A. Greiner, “A Generic Architecture for On-Chip Packet-Switched Interconnections,” Proc. Design, Automation and Test in Europe (DATE '00), pp. 250-256, Mar. 2000.
[19] P.P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, “Performance Evaluation and Design Trade-Offs for Network on Chip Interconnect Architectures,” IEEE Trans. Computers, vol. 54, no. 8, pp. 1025-1040, Aug. 2005.
[20] J. Duato, S. Yalamanchili, and L. Ni, Interconnection Networks—An Engineering Approach. Morgan Kaufmann, 2002.
[21] K. Park and W. Willinger, Self-Similar Network Traffic and Performance Evaluation. John Wiley and Sons, 2000.
[22] D.R. Avresky, V. Shubranov, R. Horst, and P. Mehra, “Performance Evaluation of the ${\rm ServerNet}^{\rm R}$ SAN under Self-Similar Traffic,” Proc. 13th Int'l and 10th Symp. Parallel and Distributed Processing (IPPS/SPDP '99), pp. 143-147, Apr. 1999.
[23] G.V. Varatkar and R. Marculescu, “On-Chip Traffic Modeling and Synthesis for MPEG-2 Video Applications,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 8, no. 3, pp. 335-339, June 2000.
[24] Circuits Multi-Projects, http:/cmp.imag.fr/, 2008.
[25] K.C. Saraswat et al., “Technology and Reliability Constrained Future Copper Interconnects—Part II: Performance Implications,” IEEE Trans. Electron Devices, vol. 49, no. 4, pp. 598-604, Apr. 2002.
[26] P.P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, “Effect of Traffic Localization on Energy Dissipation in NoC-Based Interconnect,” Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS '05), pp. 1774-1777, May 2005.

Index Terms:
Integrated Circuits, VLSI, Performance Analysis and Design Aids, Emerging technologies, System architectures, integration and modeling, Interconnection architectures, Multi-core/single-chip multiprocessors, On-chip interconnection networks
Citation:
Brett Stanley Feero, Partha Pratim Pande, "Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation," IEEE Transactions on Computers, vol. 58, no. 1, pp. 32-45, Jan. 2009, doi:10.1109/TC.2008.142
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