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A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems
December 2008 (vol. 57 no. 12)
pp. 1714-1719
ASCII Text
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Jongsun Kim, Bo-Cheng Lai, Mau-Chung Frank Chang, Ingrid Verbauwhede, "A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems," IEEE Transactions on Computers, vol. 57, no. 12, pp. 1714-1719, December, 2008.
 
 
BibTex
x
 
@article{ 10.1109/TC.2008.96,
author = {Jongsun Kim and Bo-Cheng Lai and Mau-Chung Frank Chang and Ingrid Verbauwhede},
title = {A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems},
journal ={IEEE Transactions on Computers},
volume = {57},
number = {12},
issn = {0018-9340},
year = {2008},
pages = {1714-1719},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2008.96},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems
IS - 12
SN - 0018-9340
SP1714
EP1719
EPD - 1714-1719
A1 - Jongsun Kim,
A1 - Bo-Cheng Lai,
A1 - Mau-Chung Frank Chang,
A1 - Ingrid Verbauwhede,
PY - 2008
KW - Buses
KW - Multiprocessor Systems
KW - Interconnections (Subsystems)
KW - Interconnection architectures
KW - Emerging technologies
KW - Measurement
KW - evaluation
KW - modeling
KW - simulation of multiple-processor systems
VL - 57
JA - IEEE Transactions on Computers
ER -
 
Jongsun Kim, University of California, Los Angeles, Los Angeles
Bo-Cheng Lai, University of California, Los Angeles, Los Angeles
Mau-Chung Frank Chang, University of California, Los Angeles, Los Angeles
Ingrid Verbauwhede, University of California, Los Angeles, Katholieke Universiteit Leuven, Leuven
This paper presents how a multi-core system can benefit from the use of a latency-aware memory bus capable of dual-concurrent data transfers on a single wire line: Source synchronous CDMA interconnect (SSCDMA-I) has been adopted to implement the memory bus of a shared-memory multi-core system. Two types of bus-based homogeneous and heterogeneous multi-core systems are modeled and simulated by a cycle-accurate simulation platform. Unlike the conventional time-division multiplexing (TDM) bus-based multi-core system that shows degradation in performance as the number of processing cores increases, the proposed SSCDMA bus-based multi-core shows higher performance up to 23.1% for 4 cores. The maximum latency of a heterogeneous multi-core system with a mix of traffic loads has been reduced up to 78%. These results demonstrate that the performance of multi-core systems can be improved with less cost and network complexity by reducing the bus contention interferences and by supporting higher concurrency in memory accesses that brings shorter critical word access latency.

[1] J. Kim, I. Verbauwhede, and M.F. Chang, “Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication,” IEEE Trans. VLSI Systems, vol. 15, no. 8, pp. 1-14, Aug. 2007.
[2] J. Kim, Z. Xu, and M.F. Chang, “A 2-Gbps/pin Source Synchronous CDMABus Interface with Simultaneous Multi-Chip Access and Reconfigurable I/O Capability,” Proc. IEEE Custom Integrated Circuits Conf. (CICC'03), pp. 317-320, Sept. 2003.
[3] P. Schaumont, B.C. Lai, W. Qin, and I. Verbauwhede, “Cooperative Multithreading on Embedded Multiprocessor Architectures Enables Energy-Scalable Design,” Proc. 42nd Design Automation Conf. (DAC '05), pp.27-30, June 2005.
[4] P. Schaumont, D. Ching, and I. Verbauwhede, “An Interactive Codesign Environment for Domain-Specific Coprocessors,” ACM Trans. Design Automation for Embedded Systems, Jan. 2006.
[5] J.L. Hennessy and D.A. Patterson, Computer Architecture; A Quantitative Approach. Morgan Kaufmann, 2003.
[6] V. Cuppu and B. Jacob, “Concurrency, Latency, or System Overhead: Which Has the Largest Impact on Uniprocessor DRAM-System Performance,” Proc. 28th Ann. Int'l Symp. Computer Architecture (ISCA'01), pp. 62-71, 2001.
[7] Z. Xu, H. Shin, J. Kim, M.F. Chang, and C. Chien, “Gigabit/s CDMA Interconnect Transceiver Chip-Set with Multilevel Signal Data Recovery for Reconfigurable VLSI System,” Proc. IEEE Int'l Solid-State Circuits Conf. Technical Digest (ISSCC'03), pp. 322-323, 2003.
[8] J.H. Stokes, “Understanding Bandwidth and Latency,” http://arstechnica. com/paedia/b/bandwidth-latency bandwidth-latency-1.html, 2008.
[9] B.A. Forouzan, Data Communications and Networking. McGraw-Hill, 2004.
[10] A.A. Jerraya and W. Wolf, Multiprocessor Systems-on-Chips. Morgan Kaufmann, 2005.
[11] W. Lin, S.K. Reinhardt, and D. Burger, “Designing a Modern Memory Hierarchy with Hardware Prefetching,” IEEE Trans. Computers, vol. 50, no. 11, pp. 1202-1218, Nov. 2001.

Index Terms:
Buses, Multiprocessor Systems, Interconnections (Subsystems), Interconnection architectures, Emerging technologies, Measurement, evaluation, modeling, simulation of multiple-processor systems
Citation:
Jongsun Kim, Bo-Cheng Lai, Mau-Chung Frank Chang, Ingrid Verbauwhede, "A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems," IEEE Transactions on Computers, vol. 57, no. 12, pp. 1714-1719, Dec. 2008, doi:10.1109/TC.2008.96
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