This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams
December 2008 (vol. 57 no. 12)
pp. 1633-1646
Naofumi Homma, Tohoku University, Sendai
Takafumi Aoki, Tohoku University, Sendai
Tatsuo Higuchi, Tohoku Institute of Technology, Sendai
This paper introduces a systematic approach to designing high-performance parallel adders based on Counter Tree Diagrams (CTDs). By using CTDs, we can describe addition algorithms at various levels of abstraction. A high-level CTD represents a network of coarse-grained components associated with word-level operands, whereas a low-level CTD represents a network of primitive components that can be directly mapped onto physical devices. The level of abstraction in circuit representation can be changed by decomposition of CTDs. We can derive possible variations of adder structures by decomposing a high-level CTD into low-level CTDs in a formal manner. In this paper, we focus on an application of CTDs to the design of redundant arithmetic adders with limited carry propagation. For any redundant number representation, we can obtain the optimal adder structure by trying every possible CTD decomposition and CTD-variable encoding. The potential of the proposed approach is demonstrated through an experimental synthesis of Redundant-Binary (RB) adders with CMOS standard cell libraries. We can successfully obtain RB adders that achieve an about 30-40% improvement in terms of power-delay product compared with conventional designs.

[1] I. Koren, Computer Arithmetic Algorithms, second ed. A.K. Peters, 2001.
[2] B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs. Oxford Univ. Press, 2000.
[3] T. Aoki and T. Higuchi, “Beyond-Binary Arithmetic—Algorithms and VLSI Implementations,” Interdisciplinary Information Sciences, vol. 6, no. 1, pp. 75-98, Mar. 2000.
[4] A. Avizienis, “Signed-Digit Number Representations for Fast Parallel Arithmetic,” IRE Trans. Electronic Computers, vol. 10, pp.389-400, Sept. 1961.
[5] B. Parhami, “Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations,” IEEE Trans. Computers, vol. 39, no. 1, pp. 89-98, Jan. 1990.
[6] I. Koren and Y. Maliniak, “On Classes of Positive, Negative, and Imaginary Radix Number Systems,” IEEE Trans. Computers, vol. 30, no. 5, pp. 312-317, May 1981.
[7] S.D. Phatak, T. Goff, and I. Koren, “Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations,” IEEE Trans. Computers, vol. 50, no. 11, pp. 1267-1278, Nov. 2001.
[8] J. Sakiyama, N. Homma, T. Aoki, and T. Higuchi, “Counter Tree Diagrams: A Unified Framework for Analyzing Fast Addition Algorithms,” IEICE Trans. Fundamentals, vol. E86-A, no. 12, pp.3009-3019, Dec. 2003.
[9] J. Sakiyama, T. Aoki, and T. Higuchi, “Counter Tree Diagrams for Design and Analysis of Fast Addition Algorithms,” Proc. 33rd IEEE Int'l Symp. Multiple-Valued Logic (ISMVL '03), pp. 91-98, May 2003.
[10] N. Homma, J. Sakiyama, T. Wakamatsu, T. Aoki, and T. Higuchi, “A Systematic Approach for Analyzing Fast Addition Algorithms Using Counter Tree Diagrams,” Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS '04), May 2004.
[11] N. Homma, T. Aoki, and T. Higuchi, “Algorithm-Level Interpretation of Fast Adder Structures in Binary and Multiple-Valued Logic,” Proc. 36th IEEE Int'l Symp. Multiple-Valued Logic (ISMVL '06), p. 2, May 2006.
[12] N. Homma, K. Degawa, T. Aoki, and T. Higuchi, “Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams,” Proc. 37th IEEE Int'l Symp. Multiple-Valued Logic (ISMVL '07), no. 31, pp. 1-8, May 2007.
[13] H. Makino, Y. Nakase, H. Suzuki, H. Morinaka, H. Shinohara, and K. Mashiko, “An 8.8-ns 54 $\times$ 54-Bit Multiplier with High Speed Redundant Binary Architecture,” IEEE J. Solid-State Circuits, vol. 31, no. 6, pp. 773-783, June 1996.
[14] N. Takagi, H. Yasuura, and S. Yajima, “High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree,” IEEE Trans. Computers, vol. 34, no. 9, pp. 789-796, Sept. 1985.
[15] S. Kuninobu, T. Nishiyama, and T. Taniguchi, “High Speed MOS Multiplier and Divider Using Redundant Binary Representation and Their Implementation in a Microprocessor,” IEICE Trans. Electronics, vol. E76-C, no. 3, pp. 436-445, Mar. 1993.
[16] S. Kawahito, M. Kameyama, T. Higuchi, and H. Yamada, “A 32 $\times$ 32-Bit Multiplier Using Multiple-Valued MOS Current-Mode Circuits,” IEEE J. Solid-State Circuits, vol. 23, no. 1, pp.124-132, Feb. 1988.
[17] S. Kawahito, M. Ishida, T. Nakamura, M. Kameyama, and T. Higuchi, “High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits,” IEEE Trans. Computers, vol. 43, no. 1, pp. 34-42, Jan. 1994.
[18] J. Mori, M. Nagamatsu, M. Hirano, S. Tanaka, M. Noda, Y. Toyoshima, K. Hashimoto, H. Hayashida, and K. Maeguchi, “A 10-ns 54 $\times$ 54-b Parallel Structured Full Array Multiplier with 0.5-$\mu{\rm m}$ CMOS Technology,” IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 600-606, Apr. 1991.
[19] G. Goto, T. Sato, M. Nakajima, and T. Sukemura, “A 54 $\times$ 54-b Regularly Structured Tree Multiplier,” IEEE J. Solid-State Circuits, vol. 27, no. 9, pp. 1229-1236, Sept. 1992.
[20] N. Ohkubo, M. Suzuki, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, and Y. Nakagome, “A 4.4 ns CMOS 54 $\times$ 54-b Multiplier Using Pass-Transistor Multiplexer,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 251-257, Mar. 1995.
[21] N. Takagi, “Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms,” Proc. 32nd IEEE Int'l Symp. Multiple-Valued Logic (ISMVL '02), pp. 224-235, May 2002.
[22] M. Hashimoto, K. Fujimori, and H. Onodera, “Automatic Generation of Standard Cell Library in VDSM Technologies,” Proc. Fifth Int'l Symp. Quality Electronic Design (ISQED '04), pp.36-41, Mar. 2004.

Index Terms:
Arithmetic and Logic Structures, Performance Analysis and Design Aids, High-speed Arithmetic
Citation:
Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi, "A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams," IEEE Transactions on Computers, vol. 57, no. 12, pp. 1633-1646, Dec. 2008, doi:10.1109/TC.2008.106
Usage of this product signifies your acceptance of the Terms of Use.