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Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi, "A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams," IEEE Transactions on Computers, vol. 57, no. 12, pp. 16331646, December, 2008.  
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@article{ 10.1109/TC.2008.106, author = {Naofumi Homma and Takafumi Aoki and Tatsuo Higuchi}, title = {A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams}, journal ={IEEE Transactions on Computers}, volume = {57}, number = {12}, issn = {00189340}, year = {2008}, pages = {16331646}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2008.106}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams IS  12 SN  00189340 SP1633 EP1646 EPD  16331646 A1  Naofumi Homma, A1  Takafumi Aoki, A1  Tatsuo Higuchi, PY  2008 KW  Arithmetic and Logic Structures KW  Performance Analysis and Design Aids KW  Highspeed Arithmetic VL  57 JA  IEEE Transactions on Computers ER   
[1] I. Koren, Computer Arithmetic Algorithms, second ed. A.K. Peters, 2001.
[2] B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs. Oxford Univ. Press, 2000.
[3] T. Aoki and T. Higuchi, “BeyondBinary Arithmetic—Algorithms and VLSI Implementations,” Interdisciplinary Information Sciences, vol. 6, no. 1, pp. 7598, Mar. 2000.
[4] A. Avizienis, “SignedDigit Number Representations for Fast Parallel Arithmetic,” IRE Trans. Electronic Computers, vol. 10, pp.389400, Sept. 1961.
[5] B. Parhami, “Generalized SignedDigit Number Systems: A Unifying Framework for Redundant Number Representations,” IEEE Trans. Computers, vol. 39, no. 1, pp. 8998, Jan. 1990.
[6] I. Koren and Y. Maliniak, “On Classes of Positive, Negative, and Imaginary Radix Number Systems,” IEEE Trans. Computers, vol. 30, no. 5, pp. 312317, May 1981.
[7] S.D. Phatak, T. Goff, and I. Koren, “ConstantTime Addition and Simultaneous Format Conversion Based on Redundant Binary Representations,” IEEE Trans. Computers, vol. 50, no. 11, pp. 12671278, Nov. 2001.
[8] J. Sakiyama, N. Homma, T. Aoki, and T. Higuchi, “Counter Tree Diagrams: A Unified Framework for Analyzing Fast Addition Algorithms,” IEICE Trans. Fundamentals, vol. E86A, no. 12, pp.30093019, Dec. 2003.
[9] J. Sakiyama, T. Aoki, and T. Higuchi, “Counter Tree Diagrams for Design and Analysis of Fast Addition Algorithms,” Proc. 33rd IEEE Int'l Symp. MultipleValued Logic (ISMVL '03), pp. 9198, May 2003.
[10] N. Homma, J. Sakiyama, T. Wakamatsu, T. Aoki, and T. Higuchi, “A Systematic Approach for Analyzing Fast Addition Algorithms Using Counter Tree Diagrams,” Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS '04), May 2004.
[11] N. Homma, T. Aoki, and T. Higuchi, “AlgorithmLevel Interpretation of Fast Adder Structures in Binary and MultipleValued Logic,” Proc. 36th IEEE Int'l Symp. MultipleValued Logic (ISMVL '06), p. 2, May 2006.
[12] N. Homma, K. Degawa, T. Aoki, and T. Higuchi, “AlgorithmLevel Optimization of MultipleValued Arithmetic Circuits Using Counter Tree Diagrams,” Proc. 37th IEEE Int'l Symp. MultipleValued Logic (ISMVL '07), no. 31, pp. 18, May 2007.
[13] H. Makino, Y. Nakase, H. Suzuki, H. Morinaka, H. Shinohara, and K. Mashiko, “An 8.8ns 54 $\times$ 54Bit Multiplier with High Speed Redundant Binary Architecture,” IEEE J. SolidState Circuits, vol. 31, no. 6, pp. 773783, June 1996.
[14] N. Takagi, H. Yasuura, and S. Yajima, “HighSpeed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree,” IEEE Trans. Computers, vol. 34, no. 9, pp. 789796, Sept. 1985.
[15] S. Kuninobu, T. Nishiyama, and T. Taniguchi, “High Speed MOS Multiplier and Divider Using Redundant Binary Representation and Their Implementation in a Microprocessor,” IEICE Trans. Electronics, vol. E76C, no. 3, pp. 436445, Mar. 1993.
[16] S. Kawahito, M. Kameyama, T. Higuchi, and H. Yamada, “A 32 $\times$ 32Bit Multiplier Using MultipleValued MOS CurrentMode Circuits,” IEEE J. SolidState Circuits, vol. 23, no. 1, pp.124132, Feb. 1988.
[17] S. Kawahito, M. Ishida, T. Nakamura, M. Kameyama, and T. Higuchi, “HighSpeed AreaEfficient Multiplier Design Using MultipleValued CurrentMode Circuits,” IEEE Trans. Computers, vol. 43, no. 1, pp. 3442, Jan. 1994.
[18] J. Mori, M. Nagamatsu, M. Hirano, S. Tanaka, M. Noda, Y. Toyoshima, K. Hashimoto, H. Hayashida, and K. Maeguchi, “A 10ns 54 $\times$ 54b Parallel Structured Full Array Multiplier with 0.5$\mu{\rm m}$ CMOS Technology,” IEEE J. SolidState Circuits, vol. 26, no. 4, pp. 600606, Apr. 1991.
[19] G. Goto, T. Sato, M. Nakajima, and T. Sukemura, “A 54 $\times$ 54b Regularly Structured Tree Multiplier,” IEEE J. SolidState Circuits, vol. 27, no. 9, pp. 12291236, Sept. 1992.
[20] N. Ohkubo, M. Suzuki, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, and Y. Nakagome, “A 4.4 ns CMOS 54 $\times$ 54b Multiplier Using PassTransistor Multiplexer,” IEEE J. SolidState Circuits, vol. 30, no. 3, pp. 251257, Mar. 1995.
[21] N. Takagi, “MultipleValuedDigit Number Representations in Arithmetic Circuit Algorithms,” Proc. 32nd IEEE Int'l Symp. MultipleValued Logic (ISMVL '02), pp. 224235, May 2002.
[22] M. Hashimoto, K. Fujimori, and H. Onodera, “Automatic Generation of Standard Cell Library in VDSM Technologies,” Proc. Fifth Int'l Symp. Quality Electronic Design (ISQED '04), pp.3641, Mar. 2004.