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Issue No.12 - December (2008 vol.57)

pp: 1633-1646

Naofumi Homma , Tohoku University, Sendai

Takafumi Aoki , Tohoku University, Sendai

Tatsuo Higuchi , Tohoku Institute of Technology, Sendai

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2008.106

ABSTRACT

This paper introduces a systematic approach to designing high-performance parallel adders based on Counter Tree Diagrams (CTDs). By using CTDs, we can describe addition algorithms at various levels of abstraction. A high-level CTD represents a network of coarse-grained components associated with word-level operands, whereas a low-level CTD represents a network of primitive components that can be directly mapped onto physical devices. The level of abstraction in circuit representation can be changed by decomposition of CTDs. We can derive possible variations of adder structures by decomposing a high-level CTD into low-level CTDs in a formal manner. In this paper, we focus on an application of CTDs to the design of redundant arithmetic adders with limited carry propagation. For any redundant number representation, we can obtain the optimal adder structure by trying every possible CTD decomposition and CTD-variable encoding. The potential of the proposed approach is demonstrated through an experimental synthesis of Redundant-Binary (RB) adders with CMOS standard cell libraries. We can successfully obtain RB adders that achieve an about 30-40% improvement in terms of power-delay product compared with conventional designs.

INDEX TERMS

Arithmetic and Logic Structures, Performance Analysis and Design Aids, High-speed Arithmetic

CITATION

Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi, "A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams",

*IEEE Transactions on Computers*, vol.57, no. 12, pp. 1633-1646, December 2008, doi:10.1109/TC.2008.106REFERENCES