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Issue No.12 - December (2008 vol.57)

pp: 1600-1613

Jean-Luc Beuchat , University of Tsukuba, Tsukuba

Jean-Michel Muller , ENS Lyon, Lyon

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2008.102

ABSTRACT

Since redundant number systems allow constant time addition, they are often at the heart of modular multipliers designed for public key cryptography (PKC) applications. Indeed, PKC involves large operands (160 to 1024 bits) and several researchers proposed carry-save or borrow-save algorithms. However, these number systems do not take advantage of the dedicated carry logic available in modern Field Programmable Gate Arrays (FPGAs). To overcome this problem, we suggest to perform modular multiplication in a high-radix carry-save number system, where a sum bit of the carry-save representation is replaced by a sum word. Two digits are then added by means of a small Carry-Ripple Adder (CRA). Furthermore, we propose an algorithm which selects the best high-radix carry-save representation for a given modulus, and generates a synthesizable VHDL description of the operator.

INDEX TERMS

Arithmetic and Logic Structures, High-Speed Arithmetic

CITATION

Jean-Luc Beuchat, Jean-Michel Muller, "Automatic Generation of Modular Multipliers for FPGA Applications",

*IEEE Transactions on Computers*, vol.57, no. 12, pp. 1600-1613, December 2008, doi:10.1109/TC.2008.102REFERENCES