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Automatic Generation of Modular Multipliers for FPGA Applications
December 2008 (vol. 57 no. 12)
pp. 1600-1613
Jean-Luc Beuchat, University of Tsukuba, Tsukuba
Jean-Michel Muller, ENS Lyon, Lyon
Since redundant number systems allow constant time addition, they are often at the heart of modular multipliers designed for public key cryptography (PKC) applications. Indeed, PKC involves large operands (160 to 1024 bits) and several researchers proposed carry-save or borrow-save algorithms. However, these number systems do not take advantage of the dedicated carry logic available in modern Field Programmable Gate Arrays (FPGAs). To overcome this problem, we suggest to perform modular multiplication in a high-radix carry-save number system, where a sum bit of the carry-save representation is replaced by a sum word. Two digits are then added by means of a small Carry-Ripple Adder (CRA). Furthermore, we propose an algorithm which selects the best high-radix carry-save representation for a given modulus, and generates a synthesizable VHDL description of the operator.

[1] P. Montgomery, “Modular Multiplication without Trial Division,” Math. of Computation, vol. 44, no. 170, pp. 519-521, 1985.
[2] G.R. Blakley, “A Computer Algorithm for Calculating the Product $ab$ Modulo $m$ ,” IEEE Trans. Computers, vol. 32, no. 5, pp. 497-500, May 1983.
[3] M.D. Ercegovac and T. Lang, Digital Arithmetic. Morgan Kaufmann, 2004.
[4] C.K. Koç and C.Y. Hung, “Carry-Save Adders for Computing the Product AB Modulo N,” Electronics Letters, vol. 26, no. 13, pp. 899-900, June 1990.
[5] C.K. Koç and C.Y. Hung, “A Fast Algorithm for Modular Reduction,” IEE Proc.: Computers and Digital Techniques, vol. 145, no. 4, pp. 265-271, July 1998.
[6] N. Takagi and S. Yajima, “Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem,” IEEE Trans. Computers, vol. 41, no. 7, pp. 887-891, July 1992.
[7] N. Takagi, “A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation,” IEEE Trans. Computers, vol. 41, no. 8, pp. 949-956, Aug. 1992.
[8] Y.-J. Jeong and W.P. Burleson, “VLSI Array Algorithms and Architectures for RSA Modular Multiplication,” IEEE Trans. VLSI Systems, vol. 5, no. 2, pp. 211-217, June 1997.
[9] S. Kim and G.E. Sobelman, “Digit-Serial Modular Multiplication Using Skew-Tolerant Domino CMOS,” Proc. IEEE Int'l Conf. Acoustics, Speech, and Signal Processing (ICASSP '01), vol. 2, pp.1173-1176, 2001.
[10] E. Peeters, M. Neve, and M. Ciet, “XTR Implementation on Reconfigurable Hardware,” Proc. Workshop Cryptographic Hardware and Embedded Systems (CHES '04), M. Joye and J.-J. Quisquater, eds., pp. 386-399, 2004.
[11] J.-L. Beuchat and J.-M. Muller, “Modulo $m$ Multiplication-Addition: Algorithms and FPGA Implementation,” Electronics Letters, vol. 40, no. 11, pp. 654-655, May 2004.
[12] R. Beguenane, J.-L. Beuchat, J.-M. Muller, and S. Simard, “Modular Multiplication of Large Integers on FPGA,” Proc. 39th Asilomar Conf. Signals, Systems and Computers, 2005.
[13] D.N. Amanor, C. Paar, J. Pelzl, V. Bunimov, and M. Schimmler, “Efficient Hardware Architectures for Modular Multiplication on FPGAs,” Proc. 15th Int'l Conf. Field Programmable Logic and Applications (FPL '05), pp. 539-542, 2005.

Index Terms:
Arithmetic and Logic Structures, High-Speed Arithmetic
Jean-Luc Beuchat, Jean-Michel Muller, "Automatic Generation of Modular Multipliers for FPGA Applications," IEEE Transactions on Computers, vol. 57, no. 12, pp. 1600-1613, Dec. 2008, doi:10.1109/TC.2008.102
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