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| Paul D. Fiore, "Efficient Approximate Wordlength Optimization," IEEE Transactions on Computers, vol. 57, no. 11, pp. 1561-1570, November, 2008. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.2008.87, author = {Paul D. Fiore}, title = {Efficient Approximate Wordlength Optimization}, journal ={IEEE Transactions on Computers}, volume = {57}, number = {11}, issn = {0018-9340}, year = {2008}, pages = {1561-1570}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2008.87}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Efficient Approximate Wordlength Optimization IS - 11 SN - 0018-9340 SP1561 EP1570 EPD - 1561-1570 A1 - Paul D. Fiore, PY - 2008 KW - Signal processing systems KW - Reconfigurable hardware KW - Tradeoffs between Complexity Measures KW - Multiple precision arithmetic KW - Constrained optimization VL - 57 JA - IEEE Transactions on Computers ER - | |||
[1] K. Han and B.L. Evans, “Optimum Wordlength Search Using Sensitivity Information,” EURASIP J. Applied Signal Processing, pp. 1-14, 2006.
[2] N. Herve, D. Menard, and O. Sentieys, “Data Wordlength Optimization for FPGA Synthesis,” Proc. IEEE Workshop. Signal Processing Systems Design and Implementation, pp. 623-628, Nov. 2005.
[3] G.A. Constantinides, “Perturbation Analysis for Word-Length Optimization,” Proc. 11th IEEE Symp. Field-Programmable Custom Computing Machines (FCCM), 2003.
[4] G.A. Constantinides, P.Y.K. Cheung, and W. Luk, “Wordlength Optimization for Linear Digital Signal Processing,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 10, pp. 1432-1442, Oct. 2003.
[5] K.-I. Kum and W. Sung, “Combined Word-Length Optimization and High-Level Synthesis of Digital Signal Processing Systems,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 8, pp. 921-930, Aug. 2001.
[6] M.J. Myjak and J.G. Delgado-Frias, “A Two-Level Reconfigurable Architecture for Digital Signal Processing,” Microelectronic Eng., vol. 84, no. 2, pp. 244-252, Feb. 2007.
[7] S. Roy and P. Banerjee, “An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design,” IEEE Trans. Computers, vol. 54, no. 7, pp. 886-896, July 2005.
[8] X. Liang and J.S.-N. Jean, “Mapping of Generalized Template Matching onto Reconfigurable Computers,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 11, no. 3, pp. 485-498, June 2003.
[9] P.D. Fiore, “A Custom Computing Framework for Orientation and Photogrammetry,” PhD dissertation, Massachusetts Inst. of Technology, http:/dspace.mit.edu/, Apr. 2000.
[10] J. Diaz, E. Ros, F. Pelayo, E.M. Ortigosa, and S. Mota, “FPGA-Based Real-Time Optical-Flow System,” IEEE Trans. Circuits and Systems for Video Technology, vol. 16, no. 2, pp. 274-279, Feb. 2006.
[11] Proc. First NASA/ESA Conf. Adaptive Hardware and Systems (AHS'06), A. Stoica et al., eds., June 2006.
[12] R. Weber, M. Jordan, N. Christoffers, and H.-C. Muller, “Performance of Compensation Algorithms for Direct-Conversion Receivers under Finite Wordlength Constraints,” Proc. 16th IEEE Int'l Symp. Personal, Indoor and Mobile Radio Comm. (PIMRC '05), pp. 2361-2365, 2005.
[13] D.A. Brown, “ELINT Signal Processing on Reconfigurable Computers for Detection and Classification of LPI Emitters,” PhD dissertation, Naval Postgraduate School, Monterey, Calif., June 2006.
[14] A.V. Oppenheim and R.W. Schafer, Digital Signal Processing. Prentice Hall, 1975.
[15] G.A. Constantinides, P.Y.K. Cheung, and W. Luk, “Truncation Noise in Fixed-Point SFGs,” IEE Electronics Letter, vol. 35, no. 23, pp. 2012-2014, 1999.
[16] W. Sung and K.-I. Kum, “Simulation-Based Word-Length Optimization Method for Fixed-Point Digital Signal Processing Systems,” IEEE Trans. Signal Processing, vol. 43, no. 12, pp. 3087-3090, Dec. 1995.
[17] D.-L. Lee and J.D. Villasenor, “A Bit-Width Optimization Methodology for Polynomial-Based Function Evaluation,” IEEE Trans. Computers, vol. 56, no. 4, pp. 567-571, Apr. 2007.
[18] M.-A. Cantin, “Methode de Determination Automatique de la Taille des Chemins de Donnees,” PhD dissertation, Univ. of Montreal, June 2005.
[19] G.A. Constantinides, P.Y.K. Cheung, and W. Luk, Synthesis and Optimization of DSP Algorithms. Kluwer Academic Publishers, 2004.
[20] S.C. Chan and K.M. Tsui, “Wordlength Determination Algorithms for Hardware Implementation of Linear Time Invariant Systems with Prescribed Output Accuracy,” Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS '05), vol. 3, pp. 2607-2610, May 2005.
[21] P.D. Fiore and L. Lee, “Closed-Form and Real-Time Wordlength Calculation,” Proc. IEEE Int'l Conf. Acoustics, Speech, and Signal Processing (ICASSP '99), vol. 4, pp. 1897-1900, 1999.
[22] N. Kasprzyk, J. van der Veen, and A. Koch, “Configuration Merging for Adaptive Computer Applications,” Proc. IEEE Int'l Conf. Field Programmable Logic and Applications (FPLA '05), pp. 217-222, Aug. 2005.
[23] G.R. Morris, V.K. Prasanna, and R.D. Anderson, “A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer,” Proc. 14th IEEE Symp. Field-Programmable Custom Computing Machines (FCCM'06), pp. 3-12, Apr. 2006.
[24] P.D. Fiore, C.S. Myers, J.M. Smith, and E.K. Pauer, “Rapid Implementation of Mathematical and DSP Algorithms in Configurable Computing Devices,” Proc. Configurable Computing: Technology and Applications, Part of SPIE Int'l Symp. Voice, Video and Data Comm., pp. 178-189, Nov. 1998.
[25] S. Perri, P. Corsonello, M.A. Iachino, M. Lanuzza, and G. Cocorullo, “Variable Precision Arithmetic Circuits for FPGA-Based Multimedia Processors,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 12, no. 9, pp. 995-999, Sept. 2004.
[26] E.M. Panainte, K. Bertels, and S. Vassiliadis, “Compiler-Driven FPGA-Area Allocation for Reconfigurable Computing,” Proc. Design, Automation and Test in Europe (DATE '06), Mar. 2006.
[27] J.H. Anderson and F.N. Najm, “Active Leakage Power Optimization for FPGAs,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 3, pp. 423-437, Mar. 2006.
[28] M. Goel and N.R. Shanbhag, “Low-Power Channel Coding via Dynamic Reconfiguration,” Proc. IEEE Int'l Conf. Acoustics, Speech, and Signal Processing (ICASSP '99), vol. 4, pp. 1893-1896, 1999.
[29] A. Amira and S. Chandrasekaran, “Power Modeling and Efficient FPGA Implementation of FHT for Signal Processing,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 15, no. 3, pp. 286-295, Mar. 2007.
[30] J. Stoer and R. Bulirsch, Introduction to Numerical Analysis, second ed. Springer, 1993.
[31] A.A. Gaffar, O. Mencer, W. Luk, and P.Y.K. Cheung, “Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs,” Proc. 12th IEEE Symp. Field-Programmable Custom Computing Machines (FCCM '04), Apr. 2004.
[32] S.A. Forth, “An Efficient Overloaded Implementation of Forward Mode Automatic Differentiation in MATLAB,” ACM Trans. Math. Software, vol. 33, no. 2, pp. 195-222, June 2006.
[33] M.M. Strout and P. Hovland, “Linearity Analysis for Automatic Differentiation,” Proc. Int'l Workshop Automatic Differentiation Tools and Applications (ADTA '06), May 2006.
[34] M.L. Chang and S. Hauck, “Prećis: A Usercentric Word-Length Optimization Tool,” IEEE Design and Test of Computers, vol. 22, no. 4, pp. 349-361, July/Aug. 2005.
[35] M. Willems, V. Bursgens, H. Keding, T. Grotker, and H. Meyr, “System-Level Fixed-Point Design Based on an Interpolative Approach,” Proc. 34th Conf. Design Automation (DAC '97), pp.293-298, 1997.
[36] C. Shi and R.W. Brodersen, “A Perturbation Theory on Statistical Quantization Effects in Fixed-Point DSP with Non-Stationary Inputs,” Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS '04), vol. 3, pp. 373-376, 2004.
[37] P.D. Fiore, “Efficient Wordlength Reduction Techniques for DSP Applications,” J. VLSI Signal Processing, vol. 24, no. 1, pp. 9-18, Feb. 2000.
[38] D. Bertsekas, Nonlinear Programming. Athena Scientific, 1995.
[39] D.G. Luenberger, Introduction to Dynamic Systems. John Wiley & Sons, 1979.
[40] G.W. Stewart and J. Sun, Matrix Perturbation Theory. Academic Press, 1990.
[41] H.L. Van Trees, Optimum Array Processing. Wiley Interscience, 2002.

