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Issue No.09 - September (2008 vol.57)

pp: 1289-1294

Hafizur Rahaman , University of Bristol, Bristol

Jimson Mathew , University of Bristol, Bristol

Dhiraj K. Pradhan , University of Bristol, Bristol

Abusaleh M. Jabir , University of Bristol, Bristol

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2008.63

ABSTRACT

This paper presents an algebraic testing method for detecting stuck-at faults in the polynomial basis (PB) bit parallel (BP) multiplier circuits over GF(2m). The proposed technique derives the test vectors from the expressions of the inner product (IP) variables without any requirement of ATPG tool. This low complexity testing method requires (2m+1) test vectors for detect-ing single stuck-at faults in the AND part and multiple stuck-at faults in EXOR part of the multiplier circuits. The test vectors are independent of multiplier?s structure proposed in [11] but dependant on m. For the multiplier circuits, the test set is found to be smaller in size than the ATPG-generated test set. The test set provides 100% single stuck-at fault coverage.

INDEX TERMS

Testing, stuck-at fault, Test generation, Finite fields, Polynomial basis

CITATION

Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir, "Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m)",

*IEEE Transactions on Computers*, vol.57, no. 9, pp. 1289-1294, September 2008, doi:10.1109/TC.2008.63REFERENCES