Subscribe
Issue No.09 - September (2008 vol.57)
pp: 1289-1294
Hafizur Rahaman , University of Bristol, Bristol
Jimson Mathew , University of Bristol, Bristol
Dhiraj K. Pradhan , University of Bristol, Bristol
Abusaleh M. Jabir , University of Bristol, Bristol
ABSTRACT
This paper presents an algebraic testing method for detecting stuck-at faults in the polynomial basis (PB) bit parallel (BP) multiplier circuits over GF(2m). The proposed technique derives the test vectors from the expressions of the inner product (IP) variables without any requirement of ATPG tool. This low complexity testing method requires (2m+1) test vectors for detect-ing single stuck-at faults in the AND part and multiple stuck-at faults in EXOR part of the multiplier circuits. The test vectors are independent of multiplier?s structure proposed in [11] but dependant on m. For the multiplier circuits, the test set is found to be smaller in size than the ATPG-generated test set. The test set provides 100% single stuck-at fault coverage.
INDEX TERMS
Testing, stuck-at fault, Test generation, Finite fields, Polynomial basis
CITATION
Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir, "Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m)", IEEE Transactions on Computers, vol.57, no. 9, pp. 1289-1294, September 2008, doi:10.1109/TC.2008.63
REFERENCES
 [1] T.A. Gulliver, M. Serra, and V.K. Bhargava, “The Generation of Primitive Polynomials in $GF(2^{m})$ with Independent Roots and Their Application for Power Residue Codes, VLSI Testing and Finite-Field Multipliers Using Normal Bases,” Int'l J. Electronics, vol. 71, no. 4, pp. 559-576, 1991. [2] Y. Wu and M.I. Adham, “Scan-Based BIST Fault Diagnosis,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 2, pp.203-211, 1999. [3] C.H. Wu, C.M. Wu, M.D. Sheih, and Y.T. Hwang, “High-Speed, Low-Complexity Systolic Design of Novel Iterative Division Algorithm in $GF(2^{m})$ ,” IEEE Trans. Computers, vol. 53, no. 3, pp. 375-380, Mar. 2004. [4] R.E. Blahut, Fast Algorithms for Digital Signal Processing. Addison-Wesley, 1985. [5] R. Lidl and H. Niederreiter, Introduction to Finite Fields and Their Applications. Cambridge Univ. Press, 1994. [6] I.S. Reed and X. Chen, Error-Control Coding for Data Networks. Kluwer Academic, 1999. [7] G.B. Agnew, T. Beth, R.C. Mullin, and S.A. Vanstone, “Arithmetic Operations in $GF(2^{m})$ ,” J. Cryptology, vol. 6, pp. 3-13, 1993. [8] P.A. Scott, S.J. Simmons, S.E. Tavares, and L.E. Peppard, “Architectures for Exponentiation in $GF(2^{m})$ ,” IEEE J. Selected Areas in Comm., vol. 6, no. 3, pp.578-586, Apr. 1988. [9] H. Wu and M.A. Hasan, “Efficient Exponentiation of a Primitive Root in $GF(2^{m})$ ,” IEEE Trans. Computers, vol. 46, no. 2, pp. 162-172, Feb. 1997. [10] J.H. Guo and C.L. Wang, “Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in $GF(2^{m})$ ,” IEEE Trans. Computers, vol. 47, no. 10, pp. 1161-1167, Oct. 1998. [11] A. Reyhani-Masoleh and M.A. Hasan, “Low Complexity Bit Parallel Architectures for Polynomial Basis Multiplication over $GF(2^{m})$ ,” IEEE Trans. Computers, vol. 53, no. 8, pp. 945-959, Aug. 2004. [12] T.C. Bartee and D.I. Schneider, “Computation with Finite Fields,” Information and Computers, vol. 6, pp. 79-98, Mar. 1963. [13] E.D. Mastrovito, “VLSI Designs for Multiplication over Finite Fields $GF(2^{m})$ ,” Proc. Sixth Int'l Conf. Applied Algebra, Algebraic Algorithms and Error-Correcting Codes, pp. 297-309, July 1988. [14] E.D. Mastrovito, “VLSI Architectures for Computation in Galois Fields,” PhD dissertation, Linkoping Univ., 1991. [15] B. Sunar and Ç.K. Koç, “Mastrovito Multiplier for All Trinomials,” IEEE Trans. Computers, vol. 48, no. 5, pp. 522-527, May 1999. [16] A. Halbutogullari and C.K. Koc, “Mastrovito Multiplier for General Irreducible Polynomials,” IEEE Trans. Computers, vol. 49, no. 5, pp. 503-518, May 2000. [17] D.K. Pradhan, “A Theory of Galois Switching Functions,” IEEE Trans. Computers, vol. 27, no. 3, pp. 239-248, Mar. 1978. [18] H. Rahaman, D.K. Das, and B.B. Bhattacharya, “Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults,” Proc. 17th Int'l Conf. VLSI Design, Jan. 2004. [19] H. Rahaman, D.K. Das, and B.B. Bhattacharya, “Testable Design of GRM Network with EXOR-Tree for Detecting Stuck-at and Bridging Faults,” Proc. Conf. Asia South Pacific Design Automation: Electronic Design and Solution Fair, pp. 224-229, 2004. [20] H. Fujiwara, “On Closedness and Test Complexity of Logic Circuits,” IEEE Trans. Computers, vol. 30, no. 8, pp. 556-562, Aug. 1981. [21] T. Sasao, “Easily Testable Realizations for Generalized Reed-Muller Expressions,” IEEE Trans. Computers, vol. 46, no. 6, pp. 709-716, June 1997. [22] H. Rahaman, J. Mathew, A.M. Jabir, and D.K. Pradhan, “Easily Testable Implementation for Bit Parallel Multipliers in ${\rm GF}(2^{\rm m})$ ,” Proc. 11th IEEE Int'l High-Level Design Validation and Test Workshop, 2006. [23] E.M. Sentovich et al., “SIS: A Sequential System for Sequential Circuit Synthesis,” Technical Report UCB/ERL m92/41, Electronic Research Laboratory, Univ. of California, Berkeley, May 1992. [24] A. Reyhani-Masoleh and M. Anwar Hasan, “Fault Detection Architectures for Field Multiplication Using Polynomial Bases,” IEEE Trans. Computers, vol. 55, no. 9, Sept. 2006.