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Secure Memory Accesses on Networks-on-Chip
September 2008 (vol. 57 no. 9)
pp. 1216-1229
ASCII Text
x 
 
Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic, Valerio Catalano, Cristina Silvano, "Secure Memory Accesses on Networks-on-Chip," IEEE Transactions on Computers, vol. 57, no. 9, pp. 1216-1229, September, 2008.
 
 
BibTex
x
 
@article{ 10.1109/TC.2008.69,
author = {Leandro Fiorin and Gianluca Palermo and Slobodan Lukovic and Valerio Catalano and Cristina Silvano},
title = {Secure Memory Accesses on Networks-on-Chip},
journal ={IEEE Transactions on Computers},
volume = {57},
number = {9},
issn = {0018-9340},
year = {2008},
pages = {1216-1229},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2008.69},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Secure Memory Accesses on Networks-on-Chip
IS - 9
SN - 0018-9340
SP1216
EP1229
EPD - 1216-1229
A1 - Leandro Fiorin,
A1 - Gianluca Palermo,
A1 - Slobodan Lukovic,
A1 - Valerio Catalano,
A1 - Cristina Silvano,
PY - 2008
KW - Networks-on-Chips
KW - Security
KW - Data Protection
KW - Multiprocessor System-on-Chip
VL - 57
JA - IEEE Transactions on Computers
ER -
 
Leandro Fiorin, ALaRI, Faculty of Informatics, University of Lugano, Lugano
Gianluca Palermo, Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy
Slobodan Lukovic, ALaRI, Faculty of Informatics, University of Lugano, Lugano
Valerio Catalano, ST Microelectronics, AST Grenoble Lab, France
Cristina Silvano, Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy
Security is gaining increasing relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses security aspects related to Network-on-Chip (NoC) architectures, foreseen as the communication infrastructure of next-generation embedded devices. In the context of NoC-based multiprocessor systems, we focus on the topic, not yet thoroughly faced, of data protection. In this paper, we present a secure NoC architecture composed of a set of Data Protection Units (DPUs) implemented within the Network Interfaces (NIs)\footnote{Part of this work is under patent pending}. The run-time configuration of the programmable part of the DPUs is managed by a central unit, the Network Security Manager (NSM). The DPU, similar to a firewall, can check and limit the access rights (none, read, write, or both) of processors accessing data and instructions in a shared memory - in particular distinguishing between the operating roles (supervisor/user and secure/unsecure) of the processing elements. We explore different alternative implementations for the DPU and demonstrate how this unit does not affect the network latency if the memory request has the appropriate rights. We also focus on the dynamic updating of the DPUs to support their utilization in dynamic environments, and on the utilization of authentication techniques to increase the level of security.

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Index Terms:
Networks-on-Chips, Security, Data Protection, Multiprocessor System-on-Chip
Citation:
Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic, Valerio Catalano, Cristina Silvano, "Secure Memory Accesses on Networks-on-Chip," IEEE Transactions on Computers, vol. 57, no. 9, pp. 1216-1229, Sept. 2008, doi:10.1109/TC.2008.69
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