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Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip
September 2008 (vol. 57 no. 9)
pp. 1182-1195
Anthony Leroy, Université Libre de Bruxelles, Bruxelles
Dragomir Milojevic, Université Libre de Bruxelles, Bruxelles
Diederik Verkest, Katholieke Universiteit Leuven, Belgium
Frédéric Robert, Université Libre de Bruxelles, Bruxelles
Francky Catthoor, Inter-university Micro-Electronics Center, Heverlee, Belgium
To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of widely different sizes. To interconnect the IPs of these heterogeneous platforms, Networks-on-Chip (NoC) have been proposed as an efficient and scalable alternative to shared buses. NoCs can provide throughput and latency guarantees by establishing virtual circuits between source and destination. State-of-the-art NoCs currently exploit Time-Division Multiplexing (TDM) to share network resources among virtual circuits, but this typically results in high network area and energy overhead with long circuit set-up time. We propose an alternative solution based on Spatial Division Multiplexing (SDM). This paper describes our design of an SDM-based network, discusses design alternatives for network implementation and shows why SDM can be better adapted to NoCs than TDM in a specific context. Our case study clearly illustrates the advantages of our technique over TDM in terms of energy consumption, area overhead, and flexibility. A comparison is also performed with a State-of-the-Art industrial reference NoC: Arteris.

[1] ARTERIS, http:/www.arteris.com/, 2007.
[2] Atmel, “Atmel MCU Consumes 300 $\mu{\rm A}$ at 1 MHz,” Electronic Eng. Times, Nov. 2004.
[3] A. Balakrishnan , “An Experimental Study of the Accuracy of Multiple Power Estimation Methods,” master's thesis, Univ. of Tennessee, 2004.
[4] V.E. Beneš , “On Rearrangeable Three-Stage Connecting Networks,” Bell System Technical J., vol. 41, no. 5, 1962.
[5] L. Benini and G.D. Micheli , “Networks on Chips: A New SoC Paradigm,” Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002.
[6] D. Bertozzi and L. Benini , “Xpipes: A Network-on-Chip Architecture for Gigascale Systems-on-Chip,” IEEE Circuits and Systems Magazine, vol. 4, 2004.
[7] J. Carpinelli and A. Oruc , “Applications of Edge-Coloring Algorithms to Routing in Parallel Computers,” Proc. Third Int'l Conf. Supercomputing, 1988.
[8] C. Chang and R. Melhem , “Arbitrary Size Benes Networks,” Parallel Processing Letter, 1997.
[9] C. Clos , “A Study of Nonblocking Switching Networks,” Bell System Technical J., vol. 32, pp. 406-424, 1953.
[10] W. Dally , “Route Packets, Not Wires: On-Chip Interconnection Networks,” Proc. Design Automation Conf., pp. 684-689, June 2001.
[11] P.O. de Beeck , F. Barat , M. Jayapala , and R. Lauwereins , “Crisp: A Template for Reconfigurable Instruction Set Processors,” Proc. Int'l Conf. Field Programmable Logic, 2002.
[12] J. Dielissen , A. Rădulescu , K. Goossens , and E. Rijpkema , “Concepts and Implementation of the Philips Network-on-Chip,” IP-Based SOC Design, Nov. 2003.
[13] D. Moolenaar , L. Nachtergaele , F. Catthoor , and H. Man , “System-Level Power Exploration for MPEG-2 Decoder on Embedded Cores: A Systematic Approach,” Proc. IEEE Workshop Signal Processing Systems, pp. 395-404, Nov. 1997.
[14] P. Guerrier and A. Greiner , “A Generic Architecture for On-Chip Packet-Switched Interconnections,” Proc. Design Automation and Test in Europe, pp. 250-256, 2000.
[15] A. Hemani , A. Jantsch , S. Kumar , A. Postula , J. Öberg , M. Millberg , and D. Lindqvist , “Network on Chip: An Architecture for Billion Transistor Era,” Proc. IEEE NorChip Conf., Nov. 2000.
[16] Networks on Chip, A. Jantsch and H. Tenhunen, eds. Kluwer Academic, Feb. 2003.
[17] J. Duato , S. Yalamanchili , and L.M. Ni , Interconnection Networks, An Engineering Approach. IEEE CS Press, 1998.
[18] K. Danckaert , C. Kulkarni , F. Catthoor , H. Man , and V. Tiwari , “A Systematic Approach to Reduce the System Bus Load and Power in Multi-Media Algorithms,” VLSI Design J., special issue on low power system design, vol. 12, no. 2, pp. 101-111, 2001.
[19] K. Lee , “SILENT: Serialized Low Energy Transmission Coding for On-Chip Interconnection Networks,” Proc. IEEE Int'l Conf. Computer Aided Design, pp. 448-451, Nov. 2004.
[20] B. Mei , S. Vernalde , D. Verkest , H.D. Man , and R. Lauwereins , “ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix,” Proc. Field Programmable Logic and Application, pp. 61-70, 2003.
[21] M. Millberg , E. Nilsson , R. Thid , and A. Jantsch , “Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip,” Proc. Design Automation and Test Europe Conf., Feb. 2004.
[22] D.C. Opferman and N.T. Tsao-Wu , “On a Class of Rearrangeable Switching Networks, Part I: Control Algorithms, Part II: Enumeration Studies and Fault Diagnosis,” Bell System Technical J., vol. 50, no. 5, pp. 1579-1618, May/June 1971.
[23] W. Qin , S. Rajagopalan , and S. Malik , “A Formal Concurrency Model Based Architecture Description Language for Synthesis of Software Development Tools,” Proc. ACM Conf. Languages, Compilers, and Tools for Embedded Systems, pp. 47-56, 2004.
[24] E. Rijpkema , K.G.W. Goossens , A. Rădulescu , J. Dielissen , J. van Meerbergen , P. Wielage , and E. Waterlander , “Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip,” Proc. Design, Automation and Test in Europe Conf. and Exhibition, pp. 350-355, Mar. 2003.
[25] A. Rădulescu , J. Dielissen , K. Goossens , and E. Rijpkema , “An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Programming,” Proc. Design, Automation and Test in Europe Conf. and Exhibition, pp. 878-883, Feb. 2004.
[26] A. Shickova , T. Marescaux , D. Verkest , F. Catthoor , S. Vernalde , and R. Lauwereins , “Architecture Exploration of Interconnection Networks as a Communication Layer for Reconfigurable Systems,” Proc. Ann. Workshop Circuits, Systems, and Signal Processing, 2003.
[27] P.P. Sotiriadis and A.P. Chandrakasan , “Bus Energy Reduction by Transition Pattern Coding Using a Detailed Deep Submicrometer Bus Model,” IEEE Trans. Circuits and Systems, pp. 1280-1295, 2003.
[28] S. Wilton and N.P. Jouppi , “An Enhanced Access and Cycle Time Model for On-Chip Cache,” Technical Report 93/5, DEC Western Research Laboratory, 1994.
[29] P.T. Wolkotte , G.J.M. Smit , G.K. Rauwerda , and L.T. Smit , “An Energy-Efficient Reconfigurable Circuit Switched Network-on-Chip,” Proc. IEEE Int'l Parallel and Distributed Processing Symp., p.155, 2005.

Index Terms:
Spatial Division Multiplexing, Network-on-Chip
Citation:
Anthony Leroy, Dragomir Milojevic, Diederik Verkest, Frédéric Robert, Francky Catthoor, "Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip," IEEE Transactions on Computers, vol. 57, no. 9, pp. 1182-1195, Sept. 2008, doi:10.1109/TC.2008.82
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