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Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip
September 2008 (vol. 57 no. 9)
pp. 1182-1195
Anthony Leroy, Université Libre de Bruxelles, Bruxelles
Dragomir Milojevic, Université Libre de Bruxelles, Bruxelles
Diederik Verkest, Katholieke Universiteit Leuven, Belgium
Frédéric Robert, Université Libre de Bruxelles, Bruxelles
Francky Catthoor, Inter-university Micro-Electronics Center, Heverlee, Belgium
To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of widely different sizes. To interconnect the IPs of these heterogeneous platforms, Networks-on-Chip (NoC) have been proposed as an efficient and scalable alternative to shared buses. NoCs can provide throughput and latency guarantees by establishing virtual circuits between source and destination. State-of-the-art NoCs currently exploit Time-Division Multiplexing (TDM) to share network resources among virtual circuits, but this typically results in high network area and energy overhead with long circuit set-up time. We propose an alternative solution based on Spatial Division Multiplexing (SDM). This paper describes our design of an SDM-based network, discusses design alternatives for network implementation and shows why SDM can be better adapted to NoCs than TDM in a specific context. Our case study clearly illustrates the advantages of our technique over TDM in terms of energy consumption, area overhead, and flexibility. A comparison is also performed with a State-of-the-Art industrial reference NoC: Arteris.

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Index Terms:
Spatial Division Multiplexing, Network-on-Chip
Anthony Leroy, Dragomir Milojevic, Diederik Verkest, Frédéric Robert, Francky Catthoor, "Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip," IEEE Transactions on Computers, vol. 57, no. 9, pp. 1182-1195, Sept. 2008, doi:10.1109/TC.2008.82
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