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Adaptive Channel Buffers in On-Chip Interconnection Networks— A Power and Performance Analysis
September 2008 (vol. 57 no. 9)
pp. 1169-1181
ASCII Text
x 
 
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri, "Adaptive Channel Buffers in On-Chip Interconnection Networks— A Power and Performance Analysis," IEEE Transactions on Computers, vol. 57, no. 9, pp. 1169-1181, September, 2008.
 
 
BibTex
x
 
@article{ 10.1109/TC.2008.77,
author = {Avinash Karanth Kodi and Ashwini Sarathy and Ahmed Louri},
title = {Adaptive Channel Buffers in On-Chip Interconnection Networks— A Power and Performance Analysis},
journal ={IEEE Transactions on Computers},
volume = {57},
number = {9},
issn = {0018-9340},
year = {2008},
pages = {1169-1181},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2008.77},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Adaptive Channel Buffers in On-Chip Interconnection Networks— A Power and Performance Analysis
IS - 9
SN - 0018-9340
SP1169
EP1181
EPD - 1169-1181
A1 - Avinash Karanth Kodi,
A1 - Ashwini Sarathy,
A1 - Ahmed Louri,
PY - 2008
KW - On-chip interconnection networks
KW - Interconnection architectures
KW - Low-power design
VL - 57
JA - IEEE Transactions on Computers
ER -
 
Avinash Karanth Kodi, University of Arizona, Tucson
Ashwini Sarathy, University of Arizona, Tucson
Ahmed Louri, University of Arizona, Tucson
Recent research in On-chip interconnection networks (OCINs) research has shown that the design of buffers in the router significantly influences the power, area overhead and overall performance of the network. In this paper, we propose a low-power, low-area OCIN architecture by reducing the number of buffers within the router. To minimize the performance degradation due to the reduced buffer size, we use the existing repeaters along the inter-router channels to double as buffers when required. At low network loads, the proposed adaptive channel buffers function as conventional repeaters propagating the signals. At high network loads, the adaptive channel buffers function as storage elements in addition to the router buffers. We evaluate the proposed adaptive channel buffers with both static and dynamic buffer allocation policies in the 90nm technology node, using 8?8 mesh and folded torus network topologies. Simulation results using the SPLASH-2 suite and synthetic traffic show that by reducing the router buffer size our proposed architecture achieves nearly 40% savings in router buffer power, 30% savings in overall network power and 40% savings in area, with only a marginal 1-5% drop in throughput under dynamic buffer allocation and about 10-20% drop in throughput for statically assigned buffers.

[1] L. Benini and G.D. Micheli, “Networks on Chips: A New SoC Paradigm,” Computer, vol. 35, pp. 70-78, 2002.
[2] W.J. Dally and B. Towles, “Route Packets, Not Wires: On-Chip Interconnection Networks,” Proc. Design Automation Conf., June 2001.
[3] R. Ho, K.W. Mai, and M.A. Horowitz, “The Future of Wires,” Proc. IEEE, vol. 89, pp. 490-504, Apr. 2001.
[4] L.P. Carloni and A.L. Sangiovanni-Vincentelli, “Coping with Latency in SOC Design,” IEEE Micro, vol. 22, no. 5, pp. 24-35, Sept./Oct. 2002.
[5] P.P. Pande, C. Grecu, A. Ivanov, and R. Saleh, “Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures,” IEEE Trans. Computers, vol. 54, no. 8, pp.1025-1040, Aug. 2005.
[6] S. Heo and K. Asanovic, “Replacing Global Wires with an On-Chip Network: A Power Analysis,” Proc. Int'l Symp. Low Power Electronics and Design, pp. 369-374, Aug. 2005.
[7] J. Hu and R. Marculescu, “Application-Specific Buffer Space Allocation for Network-on-Chip Router Design,” Proc. IEEE/ACM Int'l Conf. Computer Aided Design, pp. 354-361, Nov. 2004.
[8] C.A. Nicopoulos, D. Park, J. Kim, N. Vijaykrishnan, M.S. Yousif, and C.R. Das, “ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers,” Proc. 39th Ann. Int'l Symp. Microarchitecture, pp. 333-344, Dec. 2006.
[9] J. Balfour and W.J. Dally, “Design Tradeoffs for Tiled CMP On-Chip Networks,” Proc. 20th ACM Int'l Conf. Supercomputing, pp.187-198, June 2006.
[10] H.S. Wang, L.S. Peh, and S. Malik, “Power-Driven Design of Router Microarchitectures in On-Chip Networks,” Proc. 36th Ann. ACM/IEEE Int'l Symp. Microarchitecture, pp. 105-116, Dec. 2003.
[11] S. Kumar, A. Jantsch, M. Millberg, J. Oberg, J.P. Soininen, M. Forsell, K. Tiensyrja, and A. Hemani, “A Network on Chip Architecture and Design Methodology,” Proc. IEEE CS Ann. Symp. VLSI, p. 117, Apr. 2002.
[12] P. Guerrier and A. Greiner, “A Generic Architecture for On-Chip Packet-Switched Interconnections,” Proc. Conf. Design, Automation and Test in Europe, pp. 250-256, Mar. 2000.
[13] P. Kundu, “On-Die Interconnects for Next Generation CMPs,” Proc. Workshop On- and Off-Chip Interconnection Networks for Multicore Systems, Dec. 2006.
[14] J. Kim, C.A. Nicopoulos, D. Park, N. Vijaykrishnan, M.S. Yousif, and C.R. Das, “A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks,” Proc. 33rd Ann. Int'l Symp. Computer Architecture, pp. 4-15, June 2006.
[15] R. Mullins, A. West, and S. Moore, “Low-Latency Virtual Channel Routers for On-Chip Networks,” Proc. 31st Ann. Int'l Symp. Computer Architecture, pp. 188-197, June 2004.
[16] L.S. Peh and W.J. Dally, “A Delay Model and Speculative Architecture for Pipelined Routers,” Proc. Seventh Int'l Symp. High-Performance Computer Architecture, pp. 255-266, Jan. 2001.
[17] E.J. Kim, K.H. Yum, G.M. Link, N. Vijaykrishnan, M. Kandemir, M.J. Irwin, M. Yousif, and C.R. Das, “Energy Optimization Techniques in Cluster Interconnects,” Proc. Int'l Symp. Low Power Electronics and Design, pp. 459-464, Aug. 2003.
[18] L. Shang, L.S. Peh, and N.K. Jha, “Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks,” Proc. Seventh Int'l Symp. High-Performance Computer Architecture, pp. 91-102, Feb. 2003.
[19] Q. Wu, P. Juang, M. Martonosi, L.S. Peh, and D.W. Clark, “Formal Control Techniques for Power-Performance Management,” IEEE Micro, vol. 25, no. 5, Sept./Oct. 2005.
[20] J. Hu and R. Marculescu, “DyAD—Smart Routing for Networks-on-Chip,” Proc. 41st IEEE/ACM Design Automation Conf., June 2004.
[21] W.J. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann, 2004.
[22] W.J. Dally, “Virtual-Channel Flow Control,” Proc. 17th Ann. Int'l Symp. Computer Architecture, pp. 60-68, June 1990.
[23] K. Banerjee and A. Mehrotra, “A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs,” IEEE Trans. Electron Devices, vol. 49, no. 11, pp. 2001-2007, Nov. 2002.
[24] M.A. El-Moursy and E.G. Friedman, “Optimum Wire Sizing of RLC Interconnect with Repeaters,” Integration, the VLSI J., vol. 38, no. 2, pp. 205-225, Dec. 2004.
[25] M.L. Mui, K. Banerjee, and A. Mehrotra, “A Global Interconnect Optimization Scheme for Nanometer Scale VLSI with Implications for Latency, Bandwidth, and Power Dissipation,” IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 195-203, Feb. 2004.
[26] M. Mizuno, W.J. Dally, and H. Onishi, “Elastic Interconnects: Repeater-Inserted Long Wiring Capable of Compressing and Decompressing Data,” Proc. IEEE Int'l Solid-State Circuits Conf., pp.346-347, Feb. 2001.
[27] Y.M. Boura and C.R. Das, “Performance Analysis of Buffering Schemes in Wormhole Routers,” IEEE Trans. Computers, vol. 46, pp. 687-694, 1997.
[28] N. Ni, M. Pirvu, and L. Bhuyan, “Circular Buffered Switch Design with Wormhole Routing and Virtual Channels,” Proc. Int'l Conf. Computer Design, pp. 466-473, Oct. 1998.
[29] Y. Tamir and G.L. Frazier, “High-Performance Multiqueue Buffers for VLSI Communication Switches,” Proc. 15th Ann. Symp. Computer Architecture, pp. 343-354, May-June 1988.
[30] M. Rezazad and H. Sarbazi-azad, “The Effect of Virtual Channel Organization on the Performance of Interconnection Networks,” Proc. 19th Int'l Parallel and Distributed Processing Symp., Apr. 2005.
[31] H.S. Wang, X. Zhu, L.S. Peh, and S. Malik, “Orion: A Power-Performance Simulator for Interconnection Networks,” Proc. 35th Ann. ACM/IEEE Int'l Symp. Microarchitecture, pp. 294-305, Nov. 2002.
[32] C.S. Woo, M. Ohara, E. Torrie, J.P. Singh, and A. Gupta, “The SPLASH-2 Programs: Characterization and Methodological Considerations,” Proc. 22nd Ann. Int'l Symp. Computer Architecture, pp.24-37, June 1995.
[33] V. Pai, P. Ranganathan, and S.V. Adve, “RSIM Reference Manual Version 1.0,” Dept. of Electrical and Computer Eng., Rice Univ., July 1997.

Index Terms:
On-chip interconnection networks, Interconnection architectures, Low-power design
Citation:
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri, "Adaptive Channel Buffers in On-Chip Interconnection Networks— A Power and Performance Analysis," IEEE Transactions on Computers, vol. 57, no. 9, pp. 1169-1181, Sept. 2008, doi:10.1109/TC.2008.77
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