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Issue No.09 - September (2008 vol.57)
pp: 1156-1168
Chun-Hsiang Huang , National Taiwan University, Taipei
Shu-Yen Lin , National Taiwan University, Taipei
An-Yeu (Andy) Wu , National Taiwan University, Taipei
On-chip networks (OCNs) have been proposed to solve increasing scale and complexity of the designs in nano-scale multi-core VLSI designs. The concept of irregular meshes is an important issue because IPs of different sizes may be supported by various vendors. In order to solve routing problems in irregular meshes, modified routing algorithms to detour oversized IPs (OIPs) are needed. However, directly applying fault-tolerant routing algorithms may cause two serious problems: 1) heavy traffic loads around OIPs and 2) unbalanced traffic loads in irregular meshes. In this paper, we propose an OIP Avoidance Pre-Routing (OAPR) algorithm to solve the aforementioned problems. The proposed OAPR can make traffic loads evenly spread on the networks and shorten average paths of packets. Therefore, the networks using the OAPR have lower latency and higher throughput than those using fault-tolerant routing algorithms. In our experiments, four different cases are simulated to demonstrate that the proposed OAPR improves 13.3%~100% sustainable throughputs than two previous fault-tolerant routing algorithms. Moreover, the hardware overhead of the OAPR is less than 1% compared to the cost of a whole router. Hence, the proposed OAPR algorithm has good performance and is practical for irregular mesh-based OCNs.
On-chip interconnection networks, Reliability, Testing, and Fault-Tolerance
Chun-Hsiang Huang, Chih-Hao Chao, Shu-Yen Lin, An-Yeu (Andy) Wu, "Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks", IEEE Transactions on Computers, vol.57, no. 9, pp. 1156-1168, September 2008, doi:10.1109/TC.2008.60
[1] ITRS, Int'l Technology Roadmap for Semiconductors, http:/, 2008.
[2] J.A. Davis et al., “Interconnect Limits on Gigascale Integration (GSI) in the 21st Century,” Proc. IEEE, vol. 89, pp. 305-324, Mar. 2001.
[3] R. Ho, K.W. Mai, and M.A. Horowitz, “The Future of Wires,” Proc. IEEE, vol. 89, pp. 490-504, Apr. 2001.
[4] D. Sylvester and K. Keutzer, “A Global Wiring Paradigm for Deep Submicron Design,” IEEE Trans. CAD of Integrated Circuits and Systems, vol. 19, pp. 242-252, Feb. 2000.
[5] S. Kumar et al., “A Network on Chip Architecture and Design Methodology,” Proc. Int'l Symp. Very Large Scale Integration, pp.105-112, 2002.
[6] E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, “QNoC: QoS Architecture and Design Process for Network on Chip,” J. Systems Architecture, vol. 50, pp. 105-128, Feb. 2004.
[7] M.K.F Schafer, T. Hollstein, H. Zimmer, and M. Glesner, “Deadlock-Free Routing and Component Placement for Irregular Mesh-Based Networks-on-Chip,” Proc. IEEE/ACM Int'l Conf. Computer-Aided Design, pp. 238-245, 2005.
[8] K.-H. Chen and G.-M. Chiu, “Fault-Tolerant Routing Algorithm for Meshes without Using Virtual Channels,” J. Information Science and Eng., vol. 14, pp. 765-783, Dec. 1998.
[9] R.V. Boppana and S. Chalasani, “Fault-Tolerant Wormhole Routing Algorithms for Mesh Networks,” IEEE Trans. Computers, vol. 44, pp. 848-864, 1995.
[10] J. Wu, “A Fault-Tolerant and Deadlock-Free Routing Protocol in 2D Meshes Based on Odd-Even Turn Model,” IEEE Trans. Computers, vol. 52, no. 9, pp. 1154-1169, Sept. 2003.
[11] R. Holsmark and S. Kumar, “Design Issues and Performance Evaluation of Mesh NoC with Regions,” Proc. Norchip Conf., pp.40-43, 2005.
[12] G.J. Glass and L.M. Ni, “The Turn Model for Adaptive Routing,” J. ACM, vol. 40, pp. 874-902, Sept. 1994.
[13] G.M. Chiu, “The Odd-Even Turn Model for Adaptive Routing,” IEEE Trans. Parallel and Distributed Systems, vol. 11, no. 7, pp. 729-737, July 2000.
[14] J. Hu and R. Marculescu, “DyAD—Smart Routing for Networks-on-Chip,” Proc. Design Automation Conf. (DAC '04), pp. 260-263, June 2004.
[15] J. Hu and R. Marculescu, “Energy- and Performance-Aware Mapping for Regular NoC Architecture,” IEEE Trans. Computer-Aided Design of Integrated and Systems, vol. 24, pp. 551-562, Apr. 2005.
[16] D. Greenfield, A. Banerjee, J.-G. Lee, and S. Moore, “Implications of Rent's Rule for NoC Design and Its Fault-Tolerance,” Proc. ACM/IEEE Int'l Symp. Networks-on-Chip, pp. 283-294, May 2007.
[17] R. Holsmark and S. Kumar, “Corrections to Chen and Chiu's Fault Tolerant Routing Algorithm for Mesh Networks,” J.Information Science and Eng., vol. 23, pp. 1649-1662, May 2007.
[18] J. Hu and R. Marculescu, “Energy-Aware Mapping for Tile-Based NoC Architectures under Performance Constraints,” Proc. ASP Design Automation Conf., pp. 233-239, Jan. 2003.
[19] S.R. Sridhara and N.R. Shanbhag, “Coding for System-on-Chip Networks: A Unified Framework,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 13, pp. 655-667, June 2005.
[20] C. Duan, A. Tirumala, and S.P. Khatri, “Analysis and Avoidance of Cross-Talk in On-Chip Buses,” Proc. IEEE Symp. High-Performance Interconnects, pp. 133-138, Aug. 2001.
[21] S. Murali and G. De Micheli, “Bandwidth-Constrained Mapping of Cores onto NoC Architectures,” Proc. Design, Automation and Test in Europe Conf. and Exhibition, vol. 2, pp. 896-901, Feb. 2004.
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