This Article 
 Bibliographic References 
 Add to: 
A Scale Factor Correction Scheme for the CORDIC Algorithm
August 2008 (vol. 57 no. 8)
pp. 1148-1152
M.G. Buddika Sumanasena, University of Moratuwa
A method for the correction of scale factor of the CORDIC algorithm is presented in this paper. The scheme requires some additional hardware for its implementation, but does not require changing the elementary rotation angles or the sequence of iterations of the standard CORDIC algorithm. Upper bounds for the quantization error when using the proposed method are derived. A word serial implementation of the algorithm is also given. For fixed point arithmetic area and latency of the proposed implementation is compared with the standard CORDIC.

[1] J.S. Volder, “The Cordic Trigonometric Computing Technique,” IRE Trans. Electronic Computers, vol. 8, no. 3, pp. 330-334, 1959.
[2] J.E. Walther, “A Unified Algorithm for Elementary Functions,” Proc. AFIPS Spring Joint Computer Conf., vol. 38, pp. 379-385, 1971.
[3] D. Timmermann, H. Hahn, B.J. Hosticka, and B. Rix, “A New Addition Scheme and Fast Scaling Factor Compensation Methods for Cordic Algorithms,” The VLSI J. Integration, vol. 11, no. 1, pp. 85-100, Mar. 1991.
[4] A. Despain, “Fourier Transform Computers Using Cordic Iterations,” IEEE Trans. Computers, vol. 23, no. 10, pp. 993-1001, Oct. 1974.
[5] H.M. Ahmed, “Signal Processing Algorithms and Architectures,” PhD dissertation, Dept. of Electrical Eng., Stanford Univ., 1981.
[6] G.L. Haviland and A.A. Tuszynski, “A Cordic Arithmetic Processor Chip,” IEEE J. Solid State Circuits, vol. 15, no. 1, pp. 4-15, 1980.
[7] E.F. Deprettere, P. Dewilde, and R. Udo, “Pipelined Cordic Architectures for Fast VLSI Filtering and Array Processing,” Proc. IEEE Int'l Conf. Acoustics, Speech, and Signal Processing, pp. 41 A6.1-41 A6.4, 1984.
[8] R. Meyer and R. Mehling, “Architecture and Performance of a New Arithmetic Unit for the Computation of Elementary Functions,” Proc. Int'l Conf. Acoustics, Speech, and Signal Processing, pp. 1783-1786, 1990.
[9] J. Villalba, J.A. Hidalgo, E. Antelo, J.D. Bruguera, and E.L. Zapata, “Cordic Architecture with Parallel Compensation of the Scale Factor,” Proc. Int'l Conf. Application Specific Array Processors, pp. 258-269, July 1995.
[10] J. Villalba, T. Lang, and E.L. Zapata, “Parallel Compensation of Scale Factor for the Cordic Algorithm,” J. VLSI Signal Processing Systems, vol. 19, no. 3, pp. 227-241, Aug. 1998.
[11] E. Grass, B. Sarker, and K. Maharatna, “A Dual-Mode Synchronous/Asynchronous Cordic Processor,” Proc. Eighth Int'l Symp. Asynchronous Circuits and Systems, pp. 76-81, Apr. 2002.
[12] Y. Hu, “The Quantisation Effects of the Cordic Algorithm,” IEEE Trans. Signal Processing, vol. 40, no. 4, pp. 834-844, 1992.

Index Terms:
Computer arithmetic, Numerical algorithms
M.G. Buddika Sumanasena, "A Scale Factor Correction Scheme for the CORDIC Algorithm," IEEE Transactions on Computers, vol. 57, no. 8, pp. 1148-1152, Aug. 2008, doi:10.1109/TC.2008.41
Usage of this product signifies your acceptance of the Terms of Use.