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| Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, "A Current Mode, Parallel, Two-Rail Code Checker," IEEE Transactions on Computers, vol. 57, no. 8, pp. 1032-1045, August, 2008. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.2008.59, author = {Sotirios Matakias and Yiorgos Tsiatouhas and Themistoklis Haniotakis and Angela Arapoyanni}, title = {A Current Mode, Parallel, Two-Rail Code Checker}, journal ={IEEE Transactions on Computers}, volume = {57}, number = {8}, issn = {0018-9340}, year = {2008}, pages = {1032-1045}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2008.59}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - A Current Mode, Parallel, Two-Rail Code Checker IS - 8 SN - 0018-9340 SP1032 EP1045 EPD - 1032-1045 A1 - Sotirios Matakias, A1 - Yiorgos Tsiatouhas, A1 - Themistoklis Haniotakis, A1 - Angela Arapoyanni, PY - 2008 KW - Reliability KW - Testing KW - and Fault-Tolerance KW - Error-checking KW - Reliability and Testing KW - Error-checking KW - Integrated Circuits KW - VLSI KW - Reliability and Testing KW - Error-checking VL - 57 JA - IEEE Transactions on Computers ER - | |||
[1] J.W.C. Carter and P.R. Schneider, “Design of Dynamically Checked Computers,” Proc. Int'l Federation of Information Processing Congress, pp. 878-883, 1968.
[2] D.A. Anderson and G. Metze, “Design of Totally Self-Checking Circuits for $m$ -out-of-$n$ Codes,” IEEE Trans. Computers, vol. 22, pp.263-269, 1973.
[3] M. Nicolaidis and B. Courtois, “Strongly Code-Disjoint Checkers,” IEEE Trans. Computers, vol. 37, pp. 751-756, 1988.
[4] S. Tarnick, “Embedded Parity and Two-Rail TSC Checkers with Error Memorizing Capability,” Proc. IEEE On-Line Testing Workshop, pp. 221-225, 1995.
[5] C. Metra, M. Favali, and B. Ricco, “Embedded Two-Rail Checkers with On-Line Testing Ability,” Proc. IEEE VLSI Test Symp., pp.145-150, 1996.
[6] D. Nikolos, “Optimal Self-Testing Embedded Two-Rail Checkers,” Proc. IEEE On-Line Testing Workshop, pp. 154-161, 1996.
[7] D. Nikolos, “Self-Testing Embedded Two-Rail Checkers,” J.Electronic Testing: Theory and Applications, vol. 12, pp. 69-79, Feb.-Apr. 1998.
[8] S.J. Piestrac, “Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes,” IEEE Trans. Computers, vol. 51, no. 2, pp. 229-234, Feb. 2002.
[9] D. Nikolos, “Optimal Self-Testing Embedded Parity Checkers,” IEEE Trans. Computers, vol. 47, no. 3, pp. 313-321, Mar. 1998.
[10] F. Ozguner, “Design of Totally Self-Checking Embedded Two-Rail Code Checkers,” IEE Electronics Letters, vol. 27, no. 4, pp. 382-384, Feb. 1991.
[11] E. Fujiwara and K. Matsuoka, “A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing,” IEEE Trans. Computers, vol. 36, no. 1, pp. 86-93, Jan. 1987.
[12] S. Kundu and S.M. Reddy, “Embedded Totally Self-Checking Checkers: A Practical Design,” IEEE Design and Test of Computers, vol. 7, no. 4, pp. 5-12, Aug. 1990.
[13] M. Omana, D. Rossi, and C. Metra, “High Speed and Highly Testable Parallel Two-Rail Code Checker,” Proc. Design Automation and Test in Europe Conf., pp. 608-613, 2003.
[14] C. Efstathiou, “Efficient MOS Implementation of Totally Self-Checking Two-Rail Code Checkers,” Int. J. Electronics, vol. 68, no. 2, pp. 259-264, 1990.
[15] J.C. Lo, “A Novel Area-Time Efficient Static CMOS Totally Self-Checking Comparator,” IEEE J. Solid-State Circuits, vol. 28, no. 2, pp. 165-168, 1993.
[16] S. Kundu, E.S. Sogomonyan, M. Goessel, and S. Tarnick, “Self-Checking Comparator with One Periodic Output,” IEEE Trans. Computers, vol. 45, no. 3, pp. 379-380, Mar. 1996.
[17] C. Metra, M. Favali, and B. Ricco, “High Testable and Compact Single Output Comparator,” Proc. IEEE VLSI Test Symp., pp. 210-215, 1997.
[18] M. Omana, D. Rossi, and C. Metra, “Low Cost and High Speed Embedded Two-Rail Code Checker,” IEEE Trans. Computers, vol. 54, no. 2, pp. 153-164, Feb. 2005.
[19] S. Matakias, Y. Tsiatouhas, T. Haniotakis, A. Arapoyanni, and A. Efthymiou, “Fast, Parallel Two-Rail Code Checker with Enhanced Testability,” Proc. 11th IEEE Int'l On-Line Testing Symp., pp. 149-156, 2005.
[20] International Technology Roadmap for Semiconductors, http:/public.itrs.net/, 2008.
[21] R.R. Montanes, P. Volf, and J.P. de Gyvez, “Resistance Characterization for Weak Open Defects,” IEEE Design and Test of Computers, vol. 19, no. 5, pp. 18-26, Sept./Oct. 2002.
[22] J. Jahangiri and D. Abercrombie, “Value-Added Defect Testing Techniques,” IEEE Design and Test of Computers, vol. 22, no. 3, pp.224-231, May/June 2005.
[23] J.E. Smith and G. Metze, “Strongly Fault-Secure Logic Networks,” IEEE Trans. Computers, vol. 27, no. 6, pp. 491-499, June 1978.
[24] M. Nicolaidis, “Self-Exercising Checkers for Unified Built-In Self-Test (UBIST),” IEEE Trans. Computer-Aided Design, vol. 8, pp. 203-218, 1989.
[25] M. Bohr, R. Chau, T. Ghani, and K. Mistry, “The High-k Solution,” IEEE Spectrum, vol. 44, no. 10, pp. 23-29, Oct. 2007.
[26] N. Gaitanis et.al., “An Asynchronous Totally Self-Checking Two-Rail Code Error Indicator,” Proc. IEEE VLSI Test Symp., pp. 151-156, 1996.

