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Issue No.05  May (2008 vol.57)
pp: 686701
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2007.70847
ABSTRACT
This paper examines the hardware implementation tradeoffs when evaluating functions via piecewise polynomial approximations and interpolations for precisions up to 24 bits. In polynomial approximations, polynomials are evaluated using stored coefficients. Polynomial interpolations, however, require the coefficients to be computed onthefly using stored function values. Although it is known that interpolations require less memory than approximations at the expense of additional computation, the tradeoffs in memory, area, delay, and power consumption between the two approaches have not been examined in detail. This work quantitatively analyzes these tradeoffs for optimized approximations and interpolations across different functions and target precisions. Hardware architectures for degree1 and degree2 approximations and interpolations are described. The results show that the extent of memory savings realized by using interpolation is significantly lower than what is commonly believed. Furthermore, experimental results on a fieldprogrammable gate array (FPGA) show that for high output precision, degree1 interpolations offer considerable area and power savings over degree1 approximations, but similar savings are not realized when degree2 interpolations and approximations are compared. The availability of both interpolationbased and approximationbased designs offers a richer set of design tradeoffs than is available using either interpolation or approximation alone.
INDEX TERMS
Algorithms implemented in hardware, Approximation, Interpolation, VLSI Systems
CITATION
Ray Cheung, Wayne Luk, John Villasenor, "Hardware Implementation TradeOffs of Polynomial Approximations and Interpolations", IEEE Transactions on Computers, vol.57, no. 5, pp. 686701, May 2008, doi:10.1109/TC.2007.70847
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