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The European Logarithmic Microprocesor
April 2008 (vol. 57 no. 4)
pp. 532-546
In 2000 we described a proposal for a logarithmic arithmetic unit, which we suggested would offer a faster, more accurate alternative to floating-point procedures. Would it in fact do so, and could it feasibly be integrated into a microprocessor so that the intended benefits might be realised? Herein we describe the European Logarithmic Microprocessor, a device designed around that unit, and compare its performance with that of a commercial superscalar pipelined floating-point processor. We conclude that the experiment has been successful; that for 32-bit work logarithmic arithmetic may now be the technique of choice.

[1] J.N. Coleman, E.I. Chester, C. Softley, and J. Kadlec, “Arithmetic on the European Logarithmic Microprocessor,” IEEE Trans. Computers, vol. 49, no. 7, pp. 702-715, July 2000, erratum, vol.49, no. 10, p. 1152, Oct. 2000.
[2] J.N. Coleman and E.I. Chester, “A 32-Bit Logarithmic Arithmetic Unit and Its Performance Compared to Floating-Point,” Proc. 14th IEEE Symp. Computer Arithmetic, 1999.
[3] F.J. Taylor, R. Gill, J. Joseph, and J. Radke, “A 20-Bit Logarithmic Number System Processor,” IEEE Trans. Computers, vol. 37, pp.190-200, 1988.
[4] D.M. Lewis, “An Architecture for Addition and Subtraction of Long Wordlength Numbers in the Logarithmic Number System,” IEEE Trans. Computers, vol. 39, pp. 1325-1336, 1990.
[5] D. Yu and D.M. Lewis, “A 30-b Integrated Logarithmic Number System Processor,” IEEE J. Solid-State Circuits., vol. 26, pp. 1433-1440, 1991.
[6] D.M. Lewis, “Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit,” IEEE Trans. Computers, vol. 43, pp. 974-982, 1994.
[7] D.M. Lewis, “114 MFLOPS Logarithmic Number System Arithmetic Unit for DSP Applications,” IEEE J. Solid-State Circuits., vol. 30, pp. 1547-1553, 1995.
[8] V. Paliouras, J. Karagiannis, G. Aggouras, and T. Stouraitis, “A Very-Long Instruction Word Digital Signal Processor Based on the Logarithmic Number System,” Proc. Fifth IEEE Int'l Conf. Electronics, Circuits and Systems, 1998.
[9] J.N. Coleman, C.I. Softley, J. Kadlec, R. Matousek, M. Licko, Z. Pohl, and A. Hermanek, “The European Logarithmic Microprocessor—A QR RLS Application,” Proc. 35th IEEE Asilomar Conf. Signals, Systems, and Computers, 2001.
[10] M.G. Arnold, “A VLIW Architecture for Logarithmic Arithmetic,” Proc. Euromicro Symp. Digital System Design, 2003.
[11] M.G. Arnold and C. Walter, “Unrestricted Faithful Rounding Is Good Enough for Some LNS Applications,” Proc. 15th IEEE Symp. Computer Arithmetic, 2001.
[12] J.N. Coleman, C.I. Softley, J. Kadlec, R. Matousek, M. Licko, Z. Pohl, and A. Hermanek, “Performance of the European Logarithmic Microprocessor,” Proc. SPIE Ann. Meeting, 2003.
[13] C.H. Chen, R.-L. Chen, and C.-H. Yang, “Pipelined Computation of Very Large Word-Length LNS Addition/Subtraction with Polynomial Hardware Cost,” IEEE Trans. Computers, vol. 49, pp.716-726, 2000.

Index Terms:
High-Speed Arithmetic, General
Citation:
John N. Coleman, Christopher I. Softley, Jiri Kadlec, Rudolf Matousek, Milan Tichy, Z. Pohl, Antonin Hermanek, Nico F. Benschop, "The European Logarithmic Microprocesor," IEEE Transactions on Computers, vol. 57, no. 4, pp. 532-546, April 2008, doi:10.1109/TC.2007.70791
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