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Osnat Keren, "Reduction of Average Path Length in Binary Decision Diagrams by Spectral Methods," IEEE Transactions on Computers, vol. 57, no. 4, pp. 520531, April, 2008.  
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@article{ 10.1109/TC.2007.70811, author = {Osnat Keren}, title = {Reduction of Average Path Length in Binary Decision Diagrams by Spectral Methods}, journal ={IEEE Transactions on Computers}, volume = {57}, number = {4}, issn = {00189340}, year = {2008}, pages = {520531}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2007.70811}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Reduction of Average Path Length in Binary Decision Diagrams by Spectral Methods IS  4 SN  00189340 SP520 EP531 EPD  520531 A1  Osnat Keren, PY  2008 KW  Logic Design KW  Spectral methods KW  Automatic synthesis VL  57 JA  IEEE Transactions on Computers ER   
[1] J.T. Butler and T. Sasao, “On the Average Path Length in Decision Diagrams of MultipleValued Functions,” Proc. 33rd Int'l Symp. MultipleValued Logic, pp. 383390, May 2003.
[2] J.T. Butler, T. Sasao, and M. Matsuura, “Average Path Length of Binary Decision Diagrams,” IEEE Trans. Computers, vol. 54, no. 9, pp. 10411053, Sept. 2005.
[3] V. Cheushev, V. Shmerko, D.A. Simovici, and S. Yanushkevich, “Functional Entropy and Decision Trees,” Proc. 28th IEEE Int'l Symp. MultipleValued Logic, pp. 257262, May 1998.
[4] T.M. Cover and J.A. Thomas, Elements of Information Theory. WileyInterscience, 1991.
[5] E.V. Dubrova and D.M. Miller, “On Disjoint Covers and ROBDD Size,” Proc. IEEE Pacific Rim Conf. Comm., Computers, and Signal Processing, pp. 162164, 1999.
[6] R. Ebendt and R. Drechsler, “Effect of Improved Lower Bounds in Dynamic BDD Reordering,” IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 25, no. 5, pp. 902909, May 2006.
[7] B.J. Falkowski and S. Kannurao, “Calculation of Sign Walsh Spectra of Boolean Functions from Disjoint Cubes,” Proc. IEEE Int'l Symp. Circuits and Systems, vol. 5, pp. 6164, May 2001.
[8] B.J. Falkowski, I. Schafer, and M.A. Perkowski, “Calculation of the RademacherWalsh Spectrum from a Reduced Representation of Boolean Functions,” Proc. European Design Automation Conf., pp.181186, Sept. 1992.
[9] G. Fey and R. Drechsler, “Minimizing the Number of Paths in BDDs,” Proc. 15th Symp. Integrated Circuits and System Design, pp.359364, 2002.
[10] G. Fey and R. Drechsler, “Minimizing the Number of Paths in BDDs: Theory and Algorithm,” IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 25, no. 1, pp. 411, 2006.
[11] R.M. Goodman and P. Smyth, “Decision Tree Design from a Communication Theory Standpoint,” IEEE Trans. Information Theory, vol. 34, no. 5, pp. 979994, 1988.
[12] M. Hilgemeier, N. Drechsler, and R. Drechsler, “Minimizing the Number of OnePaths in BDDs by an Evolutionary Algorithm,” Proc. Congress on Evolutionary Computation, vol. 3, pp. 17241731, Dec. 2003.
[13] J. Jain, D. Moundanos, J. Bitner, J.A. Abraham, D.S. Fussell, and D.E. Ross, “Efficient Variable Ordering and Partial Representation Algorithm,” Proc. Eighth Int'l Conf. VLSI Design, pp. 8186, Jan. 1995.
[14] A.M. Kabakcioglu, P.K. Varshney, and C.R.P. Hartmann, “Application of Information Theory to Switching Function Minimisation,” IEE Proc.—Computers and Digital Techniques, vol. 137, pp.389393, Sept. 1990.
[15] M.G. Karpovsky, Finite Orthogonal Series in the Design of Digital Devices. John Wiley & Sons, 1976.
[16] M.G. Karpovsky, R.S. Stankovic, and J.T. Astola, “Reduction of Sizes of Decision Diagrams by Autocorrelation Functions,” IEEE Trans. Computers, vol. 52, no. 5, pp. 592606, May 2003.
[17] O. Keren, I. Levin, and R.S. Stankovic, “Linearization of Functions Represented as a Set of Disjoint Cubes at the Autocorrelation Domain,” Proc. Seventh Int'l Workshop Boolean Problems, pp. 137144, Sept. 2006.
[18] O. Keren, I. Levin, and R.S. Stankovic, “Reduction of the Number of Paths in Binary Decision Diagrams by Linear Transformation of Variables,” Proc. Seventh Int'l Workshop Boolean Problems, pp. 7984, Sept. 2006.
[19] A. Lioy, E. Macii, M. Poncino, and M. Rossello, “Accurate Entropy Calculation for Large Logic Circuits Based on Output Clustering,” Proc. Seventh Great Lakes Symp. VLSI, pp. 7075, 1997.
[20] Y.Y. Liu, K.H. Wang, T.T. Hwang, and C.L. Liu, “Binary Decision Diagram with Minimum Expected Path Length,” Proc. Design, Automation and Test in Europe, pp. 15301591, 2001.
[21] P.C. McGeer, K.L. McMillan, A. Saldanha, and A.L. SangiovanniVincentelli, “Fast Discrete Function Evaluation Using Decision Diagrams,” Proc. Int'l Conf. ComputerAided Design, pp. 402407, Nov. 1995.
[22] D.M. Miller, R. Drechsler, and M.A. Thornton, Spectral Techniques in VLSI CAD. Kluwer Academic, 2001.
[23] S. Nagayama, A. Mishchenko, T. Sasao, and J.T. Butler, “Minimization of Average Path Length in BDDs by Variable Reordering,” Proc. 12th Int'l Workshop Logic and Synthesis, 2003.
[24] S. Nagayama, A. Mishchenko, T. Sasao, and J.T. Butler, “Exact and Heuristic Minimization of the Average Path Length in Decision Diagrams,” J. MultiValued Logic and Soft Computing, vol. 11, pp.437465, 2005.
[25] S. Nagayama and T. Sasao, “On the Minimization of Average Path Lengths for Heterogeneous MDDs,” Proc. 34th Int'l Symp. MultipleValued Logic, pp. 216222, May 2004.
[26] S. Nagayama and T. Sasao, “On the Minimization of Longest Path Length for Decision Diagrams,” Proc. 13th Int'l Workshop Logic Synthesis, pp. 2835, June 2004.
[27] R. Rudell, “Dynamic Variable Ordering for Ordered Binary Decision Diagrams,” Proc. Int'l Conf. ComputerAided Design, pp.4247, 1993.
[28] T. Sasao, J.T. Butler, and M. Matsuuray, “Average Path Length as a Paradigm for the Fast Evaluation of Functions Represented by Binary Decision Diagrams,” Proc. First Int'l Symp. New Paradigm VLSI Computer, pp. 3136, Dec. 2002.
[29] R.S. Stankovic and B.J. Falkovski, “Spectral Interpretation of Fast Tabular Technique for FixedPolarity ReedMuller Expressions,” Int'l J. Electronics, vol. 87, no. 6, pp. 641648, June 2000.
[30] E.C. Tan and H. Yang, “Fast Tabular Technique for FixedPolarity ReedMuller Logic with Inherent Parallel Processes,” Int'l J. Electronics, vol. 85, no. 4, pp. 511520, Oct. 1998.
[31] C. Tsai and M. MarekSadowska, “Boolean Functions Classification via Fixed Polarity ReedMuller Forms,” IEEE Trans. Computers, vol. 46, no. 2, pp. 173186, Feb. 1997.
[32] D. Varma and E.A. Trachtenberg, “Design Automation Tools for Efficient Implementation of Logic Functions by Decomposition,” IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 8, no. 8, pp. 901916, Aug. 1989.
[33] “1993 LGSynth Benchmarks,” vlsicad.eecs.umich.edu/BK/Slots/cache/www.cbl.ncsu.edu/ CBL_Docslgs93.html, Mar. 1997.