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Elisardo Antelo, Julio Villalba, Emilio L. Zapata, "A LowLatency Pipelined 2D and 3D CORDIC Processors," IEEE Transactions on Computers, vol. 57, no. 3, pp. 404417, March, 2008.  
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@article{ 10.1109/TC.2007.70796, author = {Elisardo Antelo and Julio Villalba and Emilio L. Zapata}, title = {A LowLatency Pipelined 2D and 3D CORDIC Processors}, journal ={IEEE Transactions on Computers}, volume = {57}, number = {3}, issn = {00189340}, year = {2008}, pages = {404417}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2007.70796}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  A LowLatency Pipelined 2D and 3D CORDIC Processors IS  3 SN  00189340 SP404 EP417 EPD  404417 A1  Elisardo Antelo, A1  Julio Villalba, A1  Emilio L. Zapata, PY  2008 KW  Arithmetic and Logic Structures KW  HighSpeed Arithmetic KW  Algorithms KW  Computer arithmetic VL  57 JA  IEEE Transactions on Computers ER   
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