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Issue No.03 - March (2008 vol.57)

pp: 404-417

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2007.70796

ABSTRACT

The unfolded and pipelined CORDIC is a high performance hardware element that produces a wide variety of one and two argument functions with high throughput. The reduction in delay, power, and area (cost) are of significant interest regarding this module due to its high demand for resources. The linear approach to rotation has been proposed to achieve such reductions; however, the schemes for rotation (multiplication) and vectoring (division) complicate the implementation in a single unit. In this work, we improve the linear approximation scheme, leading to a unified implementation for rotation and vectoring where fully parallel tree multipliers are used instead of the second half of CORDIC iterations. We also combine the linear approximation to rotation with the scale factor compensation so that the compensation is performed concurrently with the rotation process. We then extend the method to 3D CORDIC. Such an extension is not straightforward due to the lack of existing analytical expressions for the convergence of the algorithm. A comparison using a rough area--time model and synthesis results shows that our proposals may achieve significant reductions in delay with no increase in area in actual implementations.

INDEX TERMS

Arithmetic and Logic Structures, High-Speed Arithmetic, Algorithms, Computer arithmetic

CITATION

Elisardo Antelo, Julio Villalba, Emilio L. Zapata, "A Low-Latency Pipelined 2D and 3D CORDIC Processors",

*IEEE Transactions on Computers*, vol.57, no. 3, pp. 404-417, March 2008, doi:10.1109/TC.2007.70796REFERENCES

- [2] J. Volder, “The CORDIC Computing Technique,”
IRE Trans. Electronic Computers, vol. 8, no. 3, pp. 330-334, 1959.- [3] J.S. Walther, “A Unified Algorithm for Elementary Functions,”
Proc. Spring Joint Computer Conf. '71, pp. 379-385, 1971.- [6] S.F. Hsiao, C.Y. Lau, and J.M. Delosme, “Redundant Constant-Factor Implementation of Multi-Dimensional CORDIC and Its Application to Complex SVD,”
J. VLSI Signal Processing Systems for Signal, Image, and Video Technology, special issue on CORDIC, vol.25, no. 2, pp. 155-166, June 2000.- [7] R. Andraka, “A Survey of CORDIC Algorithms for FPGAs,”
Proc. ACM/SIGDA Sixth Int'l Symp. Field Programmable Gate Arrays, pp.191-200, 1998.- [9] M. Ercegovac and T. Lang,
Digital Arithmetic. Morgan Kaufmann, 2003.- [10] http:/ieeexplore.ieee.org, 2007.
- [12] H.M. Ahmed, “Efficient Elementary Functions Generation with Multipliers,”
Proc. Ninth IEEE Symp. Computer Arithmetic, pp. 52-59, 1990.- [17] J. Villalba, T. Lang, and E.L. Zapata, “Parallel Compensation of Scale Factor for the CORDIC Algorithm,”
J. VLSI Signal Processing, vol. 19, no. 3, pp. 227-241, Aug. 1998.- [18] T. Moller and E. Haines,
Real-Time Rendering, second ed. A.K.Peters, 2002.- [19] I.E. Sutherland et al.,
Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann, 1999.- [25] J.A. Piñeiro, J.D. Bruguera, and J.M. Muller, “Faithful Powering Computation Using Table Look-Up and a Fused Accumulation Tree,”
Proc. 15th IEEE Symp. Computer Arithmetic, pp. 40-47, June 2001. |