This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Low-Transition Test Pattern Generation for BIST-Based Applications
March 2008 (vol. 57 no. 3)
pp. 303-315
ASCII Text
x 
 
Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed, "Low-Transition Test Pattern Generation for BIST-Based Applications," IEEE Transactions on Computers, vol. 57, no. 3, pp. 303-315, March, 2008.
 
 
BibTex
x
 
@article{ 10.1109/TC.2007.70794,
author = {Mehrdad Nourani and Mohammad Tehranipoor and Nisar Ahmed},
title = {Low-Transition Test Pattern Generation for BIST-Based Applications},
journal ={IEEE Transactions on Computers},
volume = {57},
number = {3},
issn = {0018-9340},
year = {2008},
pages = {303-315},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2007.70794},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Low-Transition Test Pattern Generation for BIST-Based Applications
IS - 3
SN - 0018-9340
SP303
EP315
EPD - 303-315
A1 - Mehrdad Nourani,
A1 - Mohammad Tehranipoor,
A1 - Nisar Ahmed,
PY - 2008
KW - Built-in tests
KW - Test generation
KW - Low power pattern generation
KW - Random generation
KW - Testing strategies
VL - 57
JA - IEEE Transactions on Computers
ER -
 
A low transition test pattern generator, called LT-LFSR, is proposed to reduce the average and peak power of a circuit during test by reducing the transitions among patterns. Transitions are reduced in two dimensions; 1) between consecutive patterns (fed to a combinational only circuit) and 2) between consecutive bits (sent to a scan chain in a sequential circuit). LT-LFSR is independent of circuit under test and flexible to be used in both BIST and scan-based BIST architectures. The proposed architecture reduces the correlation among the patterns generated by LT-LFSR with negligible impact on test length. The experimental results for ISCAS'85 and '89 benchmarks confirm up to 77% and 49% reduction in average and peak power, respectively.

[1] Y. Zorian, “A Distributed BIST Control Scheme for Complex VLSI Devices,” Proc. VLSI Test Symp., pp. 4-9, 1993.
[2] S. Wang and S. Gupta, “DS-LFSR: A New BIST TPG for Low Heat Dissipation,” Proc. Int'l Test Conf., pp. 848-857, 1997.
[3] F. Corno, M. Rebaudengo, M. Reorda, G. Squillero, and M. Violante, “Low Power BIST via Non-Linear Hybrid Cellular Automata,” Proc. VLSI Test Symp., pp. 29-34, 2000.
[4] P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and H.-J. Wunderlich, “A Modified Clock Scheme for a Low Power BIST Test Pattern Generator,” Proc. VLSI Test Symp., pp. 306-311, 2001.
[5] D. Gizopoulos et al., “Low Power/Energy BIST Scheme for Datapaths,” Proc. VLSI Test Symp., pp. 23-28, 2000.
[6] X. Chen and M. Hsiao, “Energy-Efficient Logic BIST Based on State Correlation Analysis,” Proc. VLSI Test Symp., pp.267-272, 2003.
[7] X. Zhang, K. Roy, and S. Bhawmik, “POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing,” Proc. Int'l Conf. VLI Design, pp. 416-422, 1999.
[8] N. Ahmed, M. Tehranipoor, and M. Nourani, “Low Power Pattern Generation for BIST Architecture,” Proc. Int'l Symp. Circuits and Systems, vol. 2, pp. 689-692, 2004.
[9] S. Wang and S. Gupta, “LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation,” Proc. Int'l Test Conf., pp. 85-94, 1999.
[10] P. Girard et al., “Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures,” Proc. Int'l Test Conf., pp. 652-661, 2000.
[11] V. Iyengar and K. Chakrabarty, “Precedence-Based, Preemptive and Power-Constrained Test Scheduling for System-on-a-Chip,” Proc. VLSI Test Symp., pp. 368-374, 2001.
[12] J. Chin and M. Nourani, “FITS: An Integrated ILP-Based Test Scheduling Environment,” IEEE Trans. Computers, vol. 54, no. 12, pp. 1598-1613, Dec. 2005.
[13] P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, J. Figueras, S. Manich, P. Teixeira, and M. Santos, “Low Energy BIST Design: Impact of the LFSR TPG Parameters on the Weighted Switching Activity,” Proc. Int'l Symp. Circuits and Systems, vol. 1, pp. 110-113, 1999.
[14] P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “A Test Vector Inhibiting Technique for Low Energy BIST Design,” Proc. VLSI Test Symp., pp. 407-412, 1999.
[15] S. Manich, A. Gabarro, M. Lopez, J. Figueras, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, P. Teixeira, and M. Santos, “Low Power BIST by Filtering Non-Detecting Vectors,” Proc. European Test Workshop, pp. 165-170, 1999.
[16] F. Corno, M. Rebaudengo, M. Sonza Reorda, and M. Violante, “A New BIST Architecture for Low Power Circuits,” Proc. European Test Workshop, pp. 160-164, 1999.
[17] A. Hertwing and H.J. Wunderlich, “Low Power Serial Built-In Self-Test,” Proc. European Test Workshop, pp. 49-53, 1998.
[18] S. Wang, “Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST,” Proc. Int'l Test Conf., pp.834-843, 2002.
[19] N. Basturkmen, S. Reddy, and I. Pomeranz, “A Low Power Pseudo-Random BIST Technique,” Proc. Int'l Conf. Computer Design, pp. 468-473, 2002.
[20] M. Tehranipoor, M. Nourani, and N. Ahmed, “Low Transition LFSR for BIST-Based Applications,” Proc. IEEE 14th Asian Test Symp., 2005.
[21] K. Butler, J. Saxena, T. Fryars, G. Hetherington, A. Jain, and J. Lewis, “Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques,” Proc. Int'l Test Conf., pp. 355-364, 2004.
[22] T. Yoshida and M. Watati, “A New Approach for Low Power Scan Testing,” Proc. Int'l Test Conf., pp. 480-487, 2003.
[23] X. Zhang and K. Roy, “Peak Power Reduction in Low Power BIST,” Proc. Int'l Symp. Quality Electronic Design, pp. 425-432, 2001.
[24] Sy nopsys, “User Manuals for SYNOPSYS Toolset Version 2002.05,” Sy nopsys, 2002.
[25] S. Manich and J. Figueras, “Sensitivity of the Worst Case Dynamic Power Estimation on Delay and Filtering Models,” Proc. Int'l Workshop Power and Timing Modeling Optimization and Simulation, 1997.
[26] P. Girard, “Survey of Low-Power Testing of VLSI Circuits,” IEEE Design and Test of Computers, vol. 19, no. 3, pp. 80-90, May-June 2002.
[27] S. Gerstendorfer and H.-J. Wunderlich, “Minimized Power Consumption for Scan-Based BIST,” Proc. Int'l Test Conf., pp. 77-84, 1999.
[28] L. Nan-Cheng, W. Sying-Jyan, and F. Yu-Hsuan Fu, “Low Power BIST with Smoother and Scan-Chain Reorder,” Proc. IEEE Asian Test Symp., pp. 40-54, 2004.
[29] M. Bellos, D. Bakalis, D. Nikolos, and X. Kavousianos, “Low Power Testing by Test Vector Ordering with Vector Repetition,” Proc. Int'l Symp. Quality Electronic Design, pp. 205-210, 2004.
[30] L. Jinkyu and N.A. Touba, “Low Power Test Data Compression Based on LFSR Reseeding,” Proc. IEEE Int'l Conf. Computer Design, pp. 180-185, 2004.
[31] Z. Sheng, S.C. Seth, and B.B. Bhattacharya, “On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design,” Proc. Int'l Conf. VLSI Design, pp. 491-496, 2005.
[32] K. Thearling and J. Abraham, “An Easily Computed Functional Level Testability Measure,” Proc. Int'l Test Conf., pp. 381-390, 1989.
[33] S. Chiu and C. Papachristou, “A Design for Testability Scheme with Applications to Datapath Synthesis,” Proc. Design Automation Conf., pp. 177-271, 1991.

Index Terms:
Built-in tests, Test generation, Low power pattern generation, Random generation, Testing strategies
Citation:
Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed, "Low-Transition Test Pattern Generation for BIST-Based Applications," IEEE Transactions on Computers, vol. 57, no. 3, pp. 303-315, March 2008, doi:10.1109/TC.2007.70794
Usage of this product signifies your acceptance of the Terms of Use.