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On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance
January 2008 (vol. 57 no. 1)
pp. 7-24
ASCII Text
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Sung Woo Chung, Kevin Skadron, "On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance," IEEE Transactions on Computers, vol. 57, no. 1, pp. 7-24, January, 2008.
 
 
BibTex
x
 
@article{ 10.1109/TC.2007.70770,
author = {Sung Woo Chung and Kevin Skadron},
title = {On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance},
journal ={IEEE Transactions on Computers},
volume = {57},
number = {1},
issn = {0018-9340},
year = {2008},
pages = {7-24},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2007.70770},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance
IS - 1
SN - 0018-9340
SP7
EP24
EPD - 7-24
A1 - Sung Woo Chung,
A1 - Kevin Skadron,
PY - 2008
KW - Cache memories
KW - Microprocessors
KW - Low-power design
KW - Energy-aware systems
VL - 57
JA - IEEE Transactions on Computers
ER -
 
This paper describes a new on-demand wakeup prediction policy for instruction cache leakage control that achieves better leakage savings than prior policies, and avoids the performance overheads of prior policies. The proposed policy reduces leakage energy by more than 92% with only less than 0.3% performance overhead on average, whereas prior policies were either prone to severe performance overhead or failed to reduce the leakage energy as much. The key to this new on-demand policy is to use branch prediction information for the wakeup prediction. In the proposed policy, inserting an extra stage for wakeup between branch prediction and fetch, allows the branch predictor to be also used as a wakeup predictor without any additional hardware. Thus, the extra stage hides the wakeup penalty, not affecting branch prediction accuracy. Though extra pipeline stages typically add to branch misprediction penalty, in this case, the extra wakeup stage on the normal fetch path can be overlapped with misprediction recovery. With such consistently accurate wakeup prediction, all cache lines except the next expected cache line(s) are in the leakage saving mode, minimizing leakage energy. We focus on super-drowsy leakage control using reduced supply voltage, because it is well suited to the instruction cache"?s criticality. The proposed policy can be applied to other leakage saving circuit techniques as long as the wakeup penalty is at most one cycle.

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Index Terms:
Cache memories, Microprocessors, Low-power design, Energy-aware systems
Citation:
Sung Woo Chung, Kevin Skadron, "On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance," IEEE Transactions on Computers, vol. 57, no. 1, pp. 7-24, Jan. 2008, doi:10.1109/TC.2007.70770
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