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Issue No.11 - November (2007 vol.56)
pp: 1549-1563
ABSTRACT
<p><b>Abstract</b>—Due to the long simulation time of the reference input set, computer architects often use reduced time simulation techniques to shorten the simulation time. However, what has not yet been thoroughly evaluated is the accuracy of these techniques relative to the reference input set and with respect to each other. To rectify this deficiency, this paper uses three methods to characterize reduced input set, truncated execution, and sampling-based simulation techniques while also examining their speed vs. accuracy trade-off and configuration dependence. Our results show that the three sampling-based techniques, SimPoint, SMARTS, and random sampling, have the best accuracy, the best speed vs. accuracy trade-off, and the least configuration dependence. On the other hand, the reduced input set and truncated execution simulation techniques had generally poor accuracy, were not significantly faster than the sampling-based techniques, and were severely configuration dependent. The final contribution of this paper is a decision tree which can help architects choose the most appropriate technique for their simulations.</p>
INDEX TERMS
Modeling of computer architecture, Measurement techniques, Modeling techniques
CITATION
Joshua J. Yi, Resit Sendag, David J. Lilja, Douglas M. Hawkins, "Speed versus Accuracy Trade-Offs in Microarchitectural Simulations", IEEE Transactions on Computers, vol.56, no. 11, pp. 1549-1563, November 2007, doi:10.1109/TC.2007.70744
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