This Article 
 Bibliographic References 
 Add to: 
On the Periodic Register Need in Software Pipelining
November 2007 (vol. 56 no. 11)
pp. 1493-1504
This paper presents several theoretical and fundamental results on the register need in periodic schedules, also known as MAXLIVE. Our first contribution is a novel formula for computing the exact number of registers needed by a scheduled loop. This formula has two advantages: Its computation can be done by using a polynomial algorithm with ${\cal O}(n \lg n)$ complexity ($n$ is the number of instructions in the loop) and it allows the generalization of a previous result [13]. Second, during software pipelining, we show that the minimal number of registers needed may increase when incrementing the initiation interval $(II)$ , which is contrary to intuition. For the case of zero architectural delays in accessing registers, we provide a sufficient condition for keeping the minimal number of registers from increasing when incrementing the $II$ . Third, we prove an interesting property that enables us to optimally compute the minimal periodic register sufficiency of a loop for all its valid periodic schedules, irrespective of $II$ . Fourth and last, we prove that the problem of optimal stage scheduling under register constraints is polynomially solvable for a subclass of data dependence graphs, whereas this problem is known to be NP-complete for arbitrary dependence graphs [7]. Our latter result generalizes a previous achievement [13] which addressed data dependence trees and forest of trees. In this study, we consider cyclic data dependence graphs without taking into account any resource constraints. The aim of our theoretical results on the periodic register need is to help current and future software pipeliners achieve significant performance improvements by making better (if not the best) use of the available resources.

[1] E. Altman, “Optimal Software Pipelining with Functional Units and Registers,” PhD dissertation, McGill Univ., Oct. 1995.
[2] D. de Werra, C. Eisenbeis, S. Lelait, and B. Marmol, “On a Graph-Theoretical Model for Cyclic Register Allocation,” Discrete Applied Math., vol. 93, nos. 2-3, pp. 191-203, July 1999.
[3] A.E. Eichenberger, E.S. Davidson, and S.G. Abraham, “Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Scheduling,” Int'l J. Parallel Programming, vol. 24, no. 2, pp.103-132, Apr. 1996.
[4] C. Eisenbeis, F. Gasperoni, and U. Schwiegelshohn, “Allocating Registers in Multiple Instruction-Issuing Processors,” Proc. IFIP WG 10.3 Working Conf. Parallel Architectures and Compilation Techniques (PACT '95), pp. 290-293, June 1995.
[5] D. Fimmel and J. Muller, “Optimal Software Pipelining under Resource Constraints,” Int'l J. Foundations of Computer Science, vol. 12, no. 6, pp. 697-718, 2001.
[6] M. Golumbic, Algorithmic Graph Theory and Perfect Graphs. Academic Press, 1980.
[7] G. Huard, “Algorithmique du Décalage d'Instructions,” PhD dissertation, École Normale Supérieure de Lyon, Dec. 2001.
[8] L.J. Hendren, G.R. Gao, E.R. Altman, and C. Mukerji, “A Register Allocation Framework Based on Hierarchical Cyclic Interval Graphs,” Lecture Notes in Computer Science, vol. 641, pp. 176-191, 1992.
[9] R. Huff, “Lifetime-Sensitive Modulo Scheduling,” Proc. ACM Conf. Programming Language Design and Implementation (PLDI '93), pp.258-267, June 1993.
[10] J. Janssen, “Compilers Strategies for Transport Triggered Architectures,” PhD dissertation, Delft Univ., 2001.
[11] C.E. Leiserson and J.B. Saxe, “Retiming Synchronous Circuitry,” Algorithmica, vol. 6, pp. 5-35, 1991.
[12] S. Lelait, “Contribution à l'Allocation de Registres dans les Boucles,” PhD dissertation, Université d'Orléans, Jan. 1996.
[13] W. Mangione-Smith, S.G. Abraham, and E.S. Davidson, “Register Requirements of Pipelined Processors,” Proc. Sixth ACM Int'l Conf. Supercomputing (ICS '92), pp. 260-271, July 1992.
[14] J. Müller, D. Fimmel, and R. Merker, “Optimal Loop Scheduling with Register Constraints Using Flow Graphs,” Proc. Seventh Int'l Symp. Parallel Architectures, Algorithms and Networks (ISPAN '04), pp. 180-186, 2004.
[15] Q. Ning and G.R. Gao, “A Novel Framework of Register Allocation for Software Pipelining,” Conf. Record 20th ACM SIGPLAN-SIGACT Symp. Principles of Programming Languages (POPL '93), pp. 29-42, Jan. 1993.
[16] B.R. Rau, M. Lee, P.P. Tirumalai, and M.S. Schlansker, “Register Allocation for Software Pipelined Loops,” SIGPLAN Notices, vol. 27, no. 7, pp. 283-299, July 1992.
[17] A. Sawaya, “Pipeline Logiciel: Découplage et Contraintes de Registres,” PhD dissertation, Université de Versailles Saint-Quentin-En-Yvelines, Apr. 1997.
[18] A. Schrijver, Theory of Linear and Integer Programming. John Wiley & Sons, 1987.
[19] R. Sethi, “Complete Register Allocation Problems,” SIAM J. Computing, vol. 4, no. 3, pp. 226-248, 1975.
[20] S.-A.-A. Touati, “Register Saturation in Instruction Level Parallelism,” Int'l J. Parallel Programming, vol. 33, no. 4, p. 57, Aug. 2005.
[21] S.-A.-A. Touati and C. Eisenbeis, “Early Periodic Register Allocation on ILP Processors,” Parallel Processing Letters, vol. 14, no. 2, June 2004.
[22] A. Tucker, “Coloring a Family of Circular Arcs,” SIAM J. Applied Math., vol. 29, no. 3, pp. 493-502, Nov. 1975.
[23] J. Wang, C. Eisenbeis, M. Jourdan, and B. Su, “Decomposed Software Pipelining: A New Perspective and a New Approach,” Int'l J. Parallel Programming, vol. 22, no. 3, pp. 351-373, June 1994.
[24] J. Wang, A. Krall, M.A. Ertl, and C. Eisenbeis, “Software Pipelining with Register Allocation and Spilling,” Proc. 27th Ann. Int'l Symp. Microarchitecture (MICRO '94), pp. 95-99, Nov. 1994.

Index Terms:
Periodic Register Requirement, MAXLIVE, Periodic Register Sufficiency, Software Pipelining, Stage Scheduling, Instruction Level Parallelism.
Sid-Ahmed-Ali Touati, "On the Periodic Register Need in Software Pipelining," IEEE Transactions on Computers, vol. 56, no. 11, pp. 1493-1504, Nov. 2007, doi:10.1109/TC.2007.70752
Usage of this product signifies your acceptance of the Terms of Use.