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Riyaz A. Patel, Mohammed Benaissa, Said Boussakta, "Fast ParallelPrefix Architectures for Modulo 2<sup>n</sup>1 Addition with a Single Representation of Zero," IEEE Transactions on Computers, vol. 56, no. 11, pp. 14841492, November, 2007.  
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@article{ 10.1109/TC.2007.70750, author = {Riyaz A. Patel and Mohammed Benaissa and Said Boussakta}, title = {Fast ParallelPrefix Architectures for Modulo 2<sup>n</sup>1 Addition with a Single Representation of Zero}, journal ={IEEE Transactions on Computers}, volume = {56}, number = {11}, issn = {00189340}, year = {2007}, pages = {14841492}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2007.70750}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  Fast ParallelPrefix Architectures for Modulo 2<sup>n</sup>1 Addition with a Single Representation of Zero IS  11 SN  00189340 SP1484 EP1492 EPD  14841492 A1  Riyaz A. Patel, A1  Mohammed Benaissa, A1  Said Boussakta, PY  2007 KW  Modulo 2n1 adders KW  One's complement adders KW  parallelprefix adders KW  computer arithmetic KW  VLSI design VL  56 JA  IEEE Transactions on Computers ER   
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