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Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero
November 2007 (vol. 56 no. 11)
pp. 1484-1492
Novel modulo 2n-1 addition algorithms for RNS applications are presented. The proposed algorithms depart from the traditional approach of modulo 2n-1 addition by setting the input carry in the first stage of the addition to one, which only ever produces one representation of zero. The resulting architectures do not only offer significant speed-up in modulo 2n-1 addition, but they can also offer a reduction in area and thus provide improvements in the cost functions area x delay2 and energy x delay. The superiority of these architectures is validated through back-annotated VLSI designs using 130nm CMOS technology.

[1] N.S. Szabo and R.I. Tanaka, Residue Arithmetic and Its Applications to Computer Technology. McGraw-Hill, 1967.
[2] M.A. Soderstrand et al., Residue Number System Arithmetic: Modern Applications in Digital Signal Processing. IEEE Press, 1986.
[3] B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs. Oxford Univ. Press, 2000.
[4] L.L. Peterson and B.S. Davie, Computer Networks: A Systems Approach. Morgan Kauffman, 2003.
[5] R.V.K. Pillai et al., “A Low Power Approach to Floating Point Adder Design,” Proc. IEEE Int'l Conf. Computer Design (ICCD '97), pp. 178-185, Oct. 1997.
[6] C. Efstathiou et al., “Area-Time Efficient Modulo $2^{n} - 1$ Adder Design,” IEEE Trans. Circuits and Systems II, vol. 41, no. 7, pp. 463-467, July 1994.
[7] A.A. Hiasat, “VLSI Implementation of New Arithmetic Residue to Binary Decoders,” IEEE Trans. Very Large Scale Integration Systems, vol. 13, no. 1, pp. 153-158, Jan. 2005.
[8] B. Cao et al., “Efficient Reverse Converters for Four-Moduli Sets $\{2^{n} - 1, 2^{n}, 2^{n} + 1, 2^{n} + 1 - 1\}$ and $\{2^{n} - 1, 2^{n}, 2^{n} + 1, 2^{n} - 1 - 1\}$ ,” IEE Proc. Computers and Digital Techniques, vol. 152, no. 5, pp. 687-696, Sept. 2005.
[9] T. Stouraitis and V. Paliouras, “Considering the Alternatives in Low-Power Design,” IEEE Circuits and Devices Magazine, vol. 17, no. 4, pp. 22-29, July 2001.
[10] G. Dimitrakopoulos et al., “A Family of Parallel-Prefix Modulo 2n- 1 Adders,” Proc. IEEE Int'l Conf. Application Specific Array Processors (ASSAP '03), pp. 315-325, June 2003.
[11] C. Efstathiou et al., “Modified Booth Modulo $2^{n} - 1$ Multipliers,” IEEE Trans. Computers, vol. 53, no. 3, pp. 370-374, Mar. 2004.
[12] S. Ming Hwa et al., “An Efficient VLSI Design for a Residue to Binary Converter for General Balance Moduli $(2^{n} - 3, 2^{n} + 1, 2^{n} - 1, 2^{n} + 3)$ ,” IEEE Trans. Circuits and Systems II, vol. 51, no. 3, pp. 152-155, Mar. 2004.
[13] R. Zimmermann, “Efficient VLSI Implementation of Modulo $(2^{n}\pm 1)$ Addition and Multiplication,” Proc. 14th Symp. Computer Arithmetic, pp. 158-167, Apr. 1999.
[14] N. Burgess, “The Flagged Prefix Adder and Its Applications in Integer Arithmetic,” J. VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 31, no. 3, pp. 263-271, July 2002.
[15] L. Kalampoukas et al., “High-Speed Parallel-Prefix Modulo $2^{n} - 1$ Adders,” IEEE Trans. Computers, vol. 49, no. 7, pp. 673-680, July 2000.
[16] G. Dimitrakopoulos et al., “A Systematic Methodology for Designing Area-Time Efficient Parallel-Prefix Modulo $2^{n} - 1$ Adders,” Proc. Int'l Symp. Circuits and Systems (ISCAS '03), vol. 5, pp. 225-228, May 2003.
[17] C. Efstathiou et al., “Modulo $2^{n}\pm 1$ Adder Design Using Select-Prefix Blocks,” IEEE Trans. Computers, vol. 52, no. 11, pp. 1399-1406, Nov. 2003.
[18] R.E. Ladner and M.J. Fischer, “Parallel Prefix Computation,” J.ACM, vol. 27, no. 4, pp. 831-838, Oct. 1980.
[19] P.M. Kogge and H.S. Stone, “A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations,” IEEE Trans. Computers, vol. 22, no. 8, pp. 786-792, Aug. 1973.
[20] S. Knowles, “A Family of Adders,” Proc. 15th IEEE Symp. Computer Arithmetic (ARITH '01), pp. 277-281, June 2001.
[21] R. Burch et al., “A Monte Carlo Approach for Power Estimation,” IEEE Trans. Very Large Scale Integration Systems, vol. 1, no. 1, pp.63-71, Mar. 1993.

Index Terms:
Modulo 2n-1 adders, One's complement adders, parallel-prefix adders, computer arithmetic, VLSI design
Citation:
Riyaz A. Patel, Mohammed Benaissa, Said Boussakta, "Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero," IEEE Transactions on Computers, vol. 56, no. 11, pp. 1484-1492, Nov. 2007, doi:10.1109/TC.2007.70750
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