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Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero
November 2007 (vol. 56 no. 11)
pp. 1484-1492
Novel modulo 2n-1 addition algorithms for RNS applications are presented. The proposed algorithms depart from the traditional approach of modulo 2n-1 addition by setting the input carry in the first stage of the addition to one, which only ever produces one representation of zero. The resulting architectures do not only offer significant speed-up in modulo 2n-1 addition, but they can also offer a reduction in area and thus provide improvements in the cost functions area x delay2 and energy x delay. The superiority of these architectures is validated through back-annotated VLSI designs using 130nm CMOS technology.

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Index Terms:
Modulo 2n-1 adders, One's complement adders, parallel-prefix adders, computer arithmetic, VLSI design
Riyaz A. Patel, Mohammed Benaissa, Said Boussakta, "Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero," IEEE Transactions on Computers, vol. 56, no. 11, pp. 1484-1492, Nov. 2007, doi:10.1109/TC.2007.70750
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