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Nicola Petra, Davide De Caro, Antonio G.M. Strollo, "A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme," IEEE Transactions on Computers, vol. 56, no. 11, pp. 14701483, November, 2007.  
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@article{ 10.1109/TC.2007.70741, author = {Nicola Petra and Davide De Caro and Antonio G.M. Strollo}, title = {A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme}, journal ={IEEE Transactions on Computers}, volume = {56}, number = {11}, issn = {00189340}, year = {2007}, pages = {14701483}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2007.70741}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme IS  11 SN  00189340 SP1470 EP1483 EPD  14701483 A1  Nicola Petra, A1  Davide De Caro, A1  Antonio G.M. Strollo, PY  2007 KW  <b>Index Terms</b>—VLSI KW  Arithmetic KW  Digital KW  HighPerformance KW  finite field multiplication KW  ReedSolomon codes KW  polynomial basis VL  56 JA  IEEE Transactions on Computers ER   
Abstract—In the paper a new GF(2^m) multiplier for standard basis representation is developed. Proposed multiplier implements the Mastrovito multiplication scheme and can be designed for every field GF(2^m). A minimum area implementation of the first block of Mastrovito multiplier and a highspeed delaydriven tree architecture for the second block of Mastrovito multiplier are employed in the new circuit. Multiplier complexity and delay are analytically evaluated for many polynomial classes. Timing and area occupation performances of the proposed multiplier are also calculated for many fields used in ReedSolomon codes applications and compared with those of previously proposed solutions. The comparison shows that the proposed multiplier outperforms previous architectures for every considered GF(2^m) field. The effectiveness of the proposed solution in a real application is verified by implementing in a 0.25?m CMOS technology the key equation solving block of a (255,239) ReedSolomon decoder. The use of the proposed multiplier in this application results in a substantial speed improvement without any penalty in silicon area occupation.
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