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Near-Memory Caching for Improved Energy Consumption
November 2007 (vol. 56 no. 11)
pp. 1441-1455

Abstract—Main memory has become one of the largest contributors to overall energy consumption and offers many opportunities for power/energy reduction. In this paper, we propose a Power-Aware Cached-DRAM (PA-CDRAM) organization that integrates a moderately sized cache directly into a memory chip. We use this near-memory cache to turn a memory bank off immediately after it is accessed to reduce power consumption.We modify the operation and structure of cached DRAM (CDRAM) with the goal of reducing energy consumption while retaining the performance advantage for which CDRAM was originally proposed. In this paper, we describe our PA-CDRAM organization and show how to incorporate it into Rambus memory. We evaluate the approach using a cycle accurate processor and memory simulator. Our results show that PA-CDRAM achieves up to 84% (28% on average) improvement in the energy-delay product and up to 76% (19% on average) savings in energy when compared to a time-out power management technique.

[1] V. Freeh, D. Lowenthal, F. Pan, N. Kappiah, and R. Springer, “Exploring the Energy-Time Tradeoff in MPI Programs on a Power-Scalable Cluster,” Proc. 19th Int'l Parallel and Distributed Processing Symp. (IPDPS '05), 2005.
[2] O. Celebican, T. Simunic, and V. Mooney, “Energy Estimation of Peripheral Devices in Embedded Systems,” Proc. 14th ACM Great Lakes Symp. VLSI (GLSVLSI '04), pp. 430-435, 2004.
[3] D. Elliott, W. Snelgrove, and M. Stumm, “Computational RAM: A Memory-SIMD Hybrid and Its Application to DSP,” Proc. IEEE Custom Integrated Circuits Conf. (CICC '92), pp. 30.6.1-30.6.4, 1992.
[4] W. Hsu and J. Smith, “Performance of Cached DRAM Organizations in Vector Supercomputers,” Proc. 20th Ann. Int'l Symp. Computer Architecture (ISCA '93), pp. 327-336, 1993.
[5] I. Kadayif, T. Chinoda, M. Kandemir, N. Vijaykirsnan, M.J. Irwin, and A. Sivasubramaniam, “vEC: Virtual Energy Counters,” Proc. ACM SIGPLAN-SIGSOFT Workshop Program Analysis for Software Tools and Eng. (PASTE '01), pp. 28-31, 2001.
[6] D. Keitel-Schulz and N. Wehn, “Embedded DRAM Development: Technology, Physical Design, and Application Issues,” IEEE Design and Test of Computers, vol. 18, no. 3, pp. 7-15, July-Sept. 2001.
[7] “NEC Embedded DRAM,” http://www.necelam.comedram90/, 2005.
[8] S. Tomashot, “IBM Embedded DRAM Approach,” productsEmbedded_ DRAM, 2003.
[9] B. Davis, “Modern Dram Architectures,” PhD dissertation, Univ. of Michigan, Ann Arbor, 2000.
[10] R. Koganti and G. Kedem, “WCDRAM: A Fully Associative Integrated Cached-DRAM with Wide Cache Lines,” technical report, Dept. of Computer Science, Duke Univ., 1997.
[11] A. Hegde, N. Vijaykrishnan, M. Kandemir, and M. Irwin, “VL-CDRAM: Variable Line Sized Cached DRAMs,” Proc. First IEEE/ACM/IFIP Int'l Symp. Hardware/Software Codesign and System Synthesis (CODES+ISSS '03), pp. 132-137, 2003.
[12] Z. Zhang, Z. Zhu, and X. Zhang, “Cached DRAM for ILP Processor Memory Access Latency Reduction,” IEEE Micro, vol. 21, no. 4, pp. 22-32, July/Aug. 2001.
[13] Rambus, “Products Data Sheets,” , 2005.
[14] A. Lebeck, X. Fan, H. Zeng, and C. Ellis, “Power Aware Page Allocation,” Proc. Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-IX), pp. 105-116, 2000.
[15] H. Huang, P. Pillai, and K. Shin, “Design and Implementation of Power-Aware Virtual Memory,” Proc. Usenix Ann. Technical Conf., pp. 57-70,, 2003.
[16] V. Delaluz and M.J. Irwin, “DRAM Energy Management Using Software and Hardware Directed Power Mode Control,” Proc. Seventh Int'l Symp. High-Performance Computer Architecture (HPCA '01), pp. 159-169, 2001.
[17] P. Shivakumar and N. Jouppi, “Cacti 3.0: An Integrated Cache Timing, Power, and Area Model,” Technical Report 2001.2, Compaq Research Laboratories, 2001.
[18] N. AbouGhazaleh, B. Childers, D. Mossé, and R. Melhem, “Near-Memory Caching for Improved Energy Consumption,” Proc. 23rd Int'l Conf. Computer Design (ICCD '05), pp. 105-110, 2005.
[19] SimpleScalar, “Architecture Simulator,” http:/www., 2004.
[20] N. AbouGhazaleh, B. Childers, D. Mossé, and R. Melhem, “Energy Conservation in Memory Hierarchies Using Power-Aware Cached-DRAM,” Proc. Dagstuhl Seminar Power-Aware Computing Systems, Apr. 2005.
[21] Y. Zhong, S. Dropsho, and C. Ding, “Miss Rate Prediction across All Program Inputs,” Proc. 12th Int'l Conf. Parallel Architectures and Compilation Techniques (PACT '03), pp. 79-90, 2003.
[22] M. Gries and A. Romer, “SDRAM and RDRAM Modeling for Simplescalar Simulator,” , 2004.
[23] W. Lin, S. Reinhardt, and D. Burger, “Reducing DRAM Latencies with an Integrated Memory Hierarchy Design,” Proc. Seventh Int'l Symp. High-Performance Computer Architecture (HPCA '01), pp. 301-312, 2001.
[24] Pentium, “Intel Pentium 4 EE Processor,” http:/, 2003.
[25] Y. Aghaghiri, F. Fallah, and M. Pedram, “Transition Reduction in Memory Buses Using Sector-Based Encoding Techniques,” IEEE Trans. Computer-Aided Design, vol. 23, no. 8, pp. 1164-1174, 2004.
[26] N. AbouGhazaleh, B. Childers, D. Mossé, and R. Melhem, “Energy Conservation in Memory Hierarchies Using Power-Aware Cached-DRAM,” Technical Report TR-05-123, Dept. of Computer Science, Univ. of Pittsburgh, 2005.
[27] Intel, “Desktop Chipset Datasheets,” index.htm, 2006.
[28] RDRAM, “RDRAM Technology Summary,” http://www.rambus. com/assets/documents/ products/RDRAMTechnologySummary_091905.pdf , 2005.
[29] J. Bond, “Memory Amnesia Could Hurt Low-Power Design,” OEG20030730 S0018, 2003.

Index Terms:
Memory design, Power Management, Energy-aware systems, Memory power management, Cached DRAM
Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem, "Near-Memory Caching for Improved Energy Consumption," IEEE Transactions on Computers, vol. 56, no. 11, pp. 1441-1455, Nov. 2007, doi:10.1109/TC.2007.70740
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