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Issue No.09 - September (2007 vol.56)
pp: 1255-1268
ABSTRACT
In this paper we analyze the conditions making Transient Faults (TFs) affecting the nodes of conventional latch structures generate output Soft-Errors (SEs). We investigate the susceptibility to TFs of all latch nodes and identify the most critical one(s). We show that, for standard latches using back-to-back inverters for their positive feedback, the internal nodes within their feedback path are the most critical. Such nodes will be hereafter referred to as internal feedback nodes. Based on this analysis, we first propose a low cost hardened latch that, compared to alternative hardened solutions, is able to filter out completely TFs affecting its internal feedback nodes, while presenting a lower susceptibility to TFs on the other internal nodes. This is achieved at the cost of a reduced robustness to TFs affecting the output node. To overcome this possible limitation (especially for systems for high reliability applications), we propose another version of our latch that, at the cost of a small area and power consumption increase compared to our first solution, improves also the robustness of the output node, which can be higher than that of alternative hardened solutions. Additionally, both proposed latches present a comparable or higher robustness of the input node than alternative solutions and provide a lower or comparable power-delay product and area overhead than classical implementations and alternative hardened solutions.
INDEX TERMS
Transient Faults, Soft Errors, Static Latch, Hardened Latch, Robust Design
CITATION
Martin Omaña, Daniele Rossi, Cecilia Metra, "Latch Susceptibility to Transient Faults and New Hardening Approach", IEEE Transactions on Computers, vol.56, no. 9, pp. 1255-1268, September 2007, doi:10.1109/TC.2007.1070
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