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Numerical Function Generators Using LUT Cascades
June 2007 (vol. 56 no. 6)
pp. 826-838
This paper proposes an architecture and a synthesis method for high-speed computation of fixed-point numerical functions such as trigonometric, logarithmic, sigmoidal, square root, and combinations of these functions. Our architecture is based on the lookup table (LUT) cascade, which results in a significant reduction in circuit complexity compared to traditional approaches. This is suitable for automatic synthesis and we show a synthesis method that converts a Matlab-like specification into an LUT cascade design. Experimental results show the efficiency of our approach as implemented on a field-programmable gate array (FPGA).
Index Terms:
LUT cascades, numerical function generators (NFGs), nonuniform segmentation, automatic synthesis, FPGA implementation.
Citation:
Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler, "Numerical Function Generators Using LUT Cascades," IEEE Transactions on Computers, vol. 56, no. 6, pp. 826-838, June 2007, doi:10.1109/TC.2007.1033
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