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Automatic Design of Area-Efficient Configurable ASIC Cores
May 2007 (vol. 56 no. 5)
pp. 662-672
Reconfigurable hardware has been shown to provide an efficient compromise between the flexibility of software and the performance of hardware. However, even coarse-grained reconfigurable architectures target the general case and miss optimization opportunities present if characteristics of the desired application set are known. Restricting the structure to support a class or a specific set of algorithms can increase efficiency while still providing flexibility within that set. By generating a custom array for a given computation domain, we explore the design space between an ASIC and an FPGA. However, the manual creation of these customized reprogrammable architectures would be a labor-intensive process, leading to high design costs. Instead, we propose automatic reconfigurable architecture generation specialized to given application sets. This paper discusses configurable ASIC (cASIC) architecture generation that creates hardware on average up to 12.3x smaller than an FPGA solution with embedded multipliers and 2.2x smaller than a standard cell implementation of individual circuits.
Index Terms:
Reconfigurable architecture, logic design and synthesis.
Citation:
Katherine Compton, Scott Hauck, "Automatic Design of Area-Efficient Configurable ASIC Cores," IEEE Transactions on Computers, vol. 56, no. 5, pp. 662-672, May 2007, doi:10.1109/TC.2007.1035
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