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Issue No.04 - April (2007 vol.56)
pp: 545-556
ABSTRACT
This paper presents a new compression technique for testing the intellectual property (IP) cores in system-on-chips. The pattern run-length compression applies the well-known run-length coding to equal and complementary consecutive patterns of the precomputed test data. No structural information of the IP cores is required by the encoding procedure. A data-independent decompressor can be realized by the embedded processor or on-chip circuitry. The decompressed test set can be flexibly applied to a single-scan or multiple-scan chain of each core-under-test. Experiments on ISCAS-89 benchmarks show that the new technique results in superior compression performance. The test application time is also significantly reduced.
INDEX TERMS
Automatic test equipment, automatic test pattern generator, embedded core testing, run-length coding, system-on-chips, test data compression.
CITATION
Xiaoyu Ruan, Rajendra S. Katti, "Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs", IEEE Transactions on Computers, vol.56, no. 4, pp. 545-556, April 2007, doi:10.1109/TC.2007.1007
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