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Miss Rate Prediction Across Program Inputs and Cache Configurations
March 2007 (vol. 56 no. 3)
pp. 328-343
Yutao Zhong, IEEE Computer Society
Chen Ding, IEEE Computer Society
Web Extra: View supplemental material
Improving cache performance requires understanding cache behavior. However, measuring cache performance for one or two data input sets provides little insight into how cache behavior varies across all data input sets and all cache configurations. This paper uses locality analysis to generate a parameterized model of program cache behavior. Given a cache size and associativity, this model predicts the miss rate for arbitrary data input set sizes. This model also identifies critical data input sizes where cache behavior exhibits marked changes. Experiments show this technique is within 2 percent of the hit rate for set associative caches on a set of floating-point and integer programs using array and pointer-based data structures. Building on the new model, this paper presents an interactive visualization tool that uses a three-dimensional plot to show miss rate changes across program data sizes and cache sizes and its use in evaluating compiler transformations. Other uses of this visualization tool include assisting machine and benchmark-set design. The tool can be accessed on the Web at http://www.cs.rochester.edu/research/locality.
Index Terms:
Cache memories, modeling techniques, performance analysis and design aids, compilers, optimization.
Citation:
Yutao Zhong, Steven G. Dropsho, Xipeng Shen, Ahren Studer, Chen Ding, "Miss Rate Prediction Across Program Inputs and Cache Configurations," IEEE Transactions on Computers, vol. 56, no. 3, pp. 328-343, March 2007, doi:10.1109/TC.2007.50
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