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Lightweight Error Correction Coding for System-Level Interconnects
March 2007 (vol. 56 no. 3)
pp. 289-304
"Lightweight Hierarchical Error Control Coding (LHECC)” is a new class of nonlinear block codes that is designed to increase noise immunity and decrease error rate for high-performance chip-to-chip and on-chip interconnects. LHECC is designed such that its corresponding encoder and decoder logic may be tightly integrated into compact, high-speed, and low-latency I/O interfaces. LHECC operates over a new channel technology called Multi-Bit Differential Signaling (MBDS). MBDS channels utilize a physical-layer channel code called "N choose M (nCm)” encoding, where each channel is restricted to a symbol set such that half of the bits in each symbol are set to one. These symbol sets have properties that are utilized by LHECC to achieve error correction capability while requiring low or zero relative information overhead. In addition, these codes may be designed such that the latency and size of the corresponding decoders are tightly bounded. The effectiveness of these codes is demonstrated by modeling error behavior of MBDS interconnects over a range of transmission rates and noise characteristics.
Index Terms:
Interconnections (subsystems), interconnection architectures, code design, coding tools and techniques, coding and information theory, error control codes.
Citation:
Jason D. Bakos, Donald M. Chiarulli, Steven P. Levitan, "Lightweight Error Correction Coding for System-Level Interconnects," IEEE Transactions on Computers, vol. 56, no. 3, pp. 289-304, March 2007, doi:10.1109/TC.2007.49
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