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Issue No.02 - February (2007 vol.56)
pp: 243-252
Kaijie Wu , IEEE
ABSTRACT
Errors introduced by radiation-induced single event upset and single event latchup in very deep submicron (VDSM) ICs necessitate concurrent error detection (CED) and correction. Power consumed by circuits used for detecting and correcting errors becomes an extra burden on the tight power budget of VDSM ICs. The triple-modular redundancy-based fault tolerance technique, which is traditionally used for error detection and correction, incurs over 200 percent power overhead. In this paper, we propose register-transfer level low-power on-demand error correction techniques. Proposed techniques implement an original computation and a recomputation in datapath and compare the results from two computations to monitor the health of circuit. A mismatch in results indicates faulty computation and a second recomputation is triggered to rectify the error. The proposed techniques can detect and correct SEU induced transient errors and detect SEL induced permanent errors with as little as 12 percent power overhead.
INDEX TERMS
Concurrent error detection, single-event upsets, register-transfer level, hardware redundancy.
CITATION
Piyush Mishra, Kaijie Wu, "Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique", IEEE Transactions on Computers, vol.56, no. 2, pp. 243-252, February 2007, doi:10.1109/TC.2007.27
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