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Architecture of a Self-Checkpointing Microprocessor that Incorporates Nanomagnetic Devices
February 2007 (vol. 56 no. 2)
pp. 161-173
Memory and latch circuits in CMOS systems rely on capacitatively-stored charge to hold state information. When power is removed from a chip, this charge quickly drains off, destroying any information that was contained in the chip. This causes a number of problems for computer systems, including data loss from power failures, the need to load operating systems from nonvolatile storage each time the system is powered on, and high "idle” power consumption due to leakage currents in memory arrays. Magnetoelectronic devices that combine ferromagnetic elements with semiconductor structures have the potential to overcome this limitation by providing high-performance nonvolatile storage that can be tightly integrated with logic. In this paper, we present the architecture of a microprocessor that uses magnetoelectronic devices to "snapshot” the state of the currently executing program at regular intervals. If its power supply is interrupted, this self-checkpointing microprocessor can near instantly restore its state from the last checkpoint, allowing it to resume execution with little loss of progress. Simulations of a self-checkpointing version of the Pentium 4 microprocessor show that the magnetoelectronic memories increase power consumption by only 62 mW, with little to no cost in system performance.

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Index Terms:
Emerging technologies, memory technologies, low-power design.
Citation:
Love Kothari, Nicholas P. Carter, "Architecture of a Self-Checkpointing Microprocessor that Incorporates Nanomagnetic Devices," IEEE Transactions on Computers, vol. 56, no. 2, pp. 161-173, Feb. 2007, doi:10.1109/TC.2007.21
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