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Opens and Delay Faults in CMOS RAM Address Decoders
December 2006 (vol. 55 no. 12)
pp. 1630-1639
ASCII Text
x 
 
Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, "Opens and Delay Faults in CMOS RAM Address Decoders," IEEE Transactions on Computers, vol. 55, no. 12, pp. 1630-1639, December, 2006.
 
 
BibTex
x
 
@article{ 10.1109/TC.2006.203,
author = {Said Hamdioui and Zaid Al-Ars and Ad J. van de Goor},
title = {Opens and Delay Faults in CMOS RAM Address Decoders},
journal ={IEEE Transactions on Computers},
volume = {55},
number = {12},
issn = {0018-9340},
year = {2006},
pages = {1630-1639},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2006.203},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Opens and Delay Faults in CMOS RAM Address Decoders
IS - 12
SN - 0018-9340
SP1630
EP1639
EPD - 1630-1639
A1 - Said Hamdioui,
A1 - Zaid Al-Ars,
A1 - Ad J. van de Goor,
PY - 2006
KW - Memory testing
KW - open defects
KW - address decoder delay faults
KW - addressing methods
KW - BIST
KW - DFT.
VL - 55
JA - IEEE Transactions on Computers
ER -
 
This paper presents a complete electrical analysis of Address decoder Delay Faults "ADFs” caused by resistive opens in RAMs. A classification between inter and intragate opens is made. A systematic way is introduced to explore the space of possible tests to detect these faults; it is based on generating appropriate sensitizing address transitions and the corresponding sensitizing operation sequences. DFT features are given to facilitate the BIST implementation of the new tests.

[1] R.D. Adams and E.S. Cooley, “Analysis of Deceptive Destructive Read Memory Fault Model and Recommended Testing,” Records North Atlantic Test Workshop, pp. 27-32, May 1996.
[2] R.D. Adams and E.S. Cooley, “False Write Through and Un-Restored Write Electrical Level Faults Models for SRAMs,” Proc. IEEE Int'l Workshop Memory Technology, Design, and Testing (MTDT), pp. 27-32, 1997.
[3] M. Azimane and A.K. Majhi, “New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders,” Proc. IEEE VLSI Test Symp., pp. 123-128, 2004.
[4] J.H. de Jonge and A.J. Smeulders, “Moving Inversion Test Pattern Is Thorough, Yet Speedy,” Computer Design, pp. 169-173, May 1976.
[5] L. Dilillo et al., “Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders,” Proc. IEEE Asian Test Symp., pp. 250-255, 2003.
[6] L. Dilillo et al., “March iC-: An Improved Version of March C- for ADOFs Detection,” Proc. IEEE VLSI Test Symp., pp. 129-134, 2004.
[7] M.T. Fragano, J.H. Oppold, M.R. Ouellette, and J.P. Rowland, “Self-Test Pattern to Detect Stuck-Open Faults,” US Patent No. 6,442,085 B1, 27 Aug. 2002.
[8] E. Gizdarsky, “Detection of Delay Faults in Memory Address Decoders,” J. Electronic Testing: Theory and Applications, vol. 16, pp.381-387, 2000.
[9] S. Hamdioui, Testing Static Random Access Memories: Defects, Fault Models, and Test Patterns. Boston: Kluwer Academic, Mar. 2004.
[10] S. Hamdioui, A.J. van de Goor, and M. Rodgers, “March SS: A Test for All Static Simple RAM Faults,” Proc. IEEE Int'l Workshop Memory Technology, Design and Testing, pp. 95-100, 2002.
[11] N. Jha and S. Gupta, Testing of Digital Systems. Cambridge Univ. Press, 2003.
[12] M. Klaus and A.J. van de Goor, “Tests for Resistive and Capacitive Defects in Address Decoders,” Proc. Asian Test Symp., pp. 31-36, 2001.
[13] S. Kundu et al., “Test Challenges in Nanometer Technologies,” J.Electronic Testing: Theory and Applications, vol. 17, nos. 3/4, pp.209-218, 2001.
[14] M. Marinescu, “Simple and Eficient Algorithms for Functional RAM Testing,” Proc. IEEE Int'l Test Conf., pp. 236-239, 1982.
[15] B. Nadeau-Dostie et al., “Serial Interfacing for Embedded-Memory Testing,” IEEE Design and Test of Computers, vol. 7, no. 2, pp. 52-63, 1990.
[16] R. Nair, “An Optimal Algorithm for Testing Stuck-At Faults Random Access Memories,” IEEE Trans. Computers, vol. 8, no. 3, pp. 258-261, Mar. 1978.
[17] S. Nakahara et al., “Built-In Self-Test for GHz Embedded SRAMs Using Flexible Pattern Generator and New Repair Algorithm,” Proc. IEEE Int'l Test Conf., pp. 301-310, 1999.
[18] W. Needham et al., “High Volume Microprocessor Test Escapes, an Analysis Our Tests Are Missing,” Proc. IEEE Int'l Test Conf., pp.25-34, 1998.
[19] P. Nigh and A. Gattiker, “Test Method Evaluation Experiments & Data,” Proc. IEEE Int'l Test Conf., pp. 454-463, 2000.
[20] J. Otterstedt et al., “Detection of CMOS Address Decoder Open Faults with March and Pseudo Random Memory Tests,” Proc. IEEE Int'l Test Conf., pp. 53-62, 1998.
[21] T.R.N. Rao and E. Fujiwara, Error-Control Coding for Computer Systems. Prentice-Hall, 1989.
[22] M. Sachdev, “Open Defects in CMOS RAM Address Decoders,” IEEE Design and Test of Computers, pp. 26-33, Apr.-June 1997.
[23] M. Sachdev, “Test and Testability Techniques for Open Defects in CMOS RAM Address Decoders,” Proc. European Design and Test Conf., pp. 428-434, 1996.
[24] A.J. van de Goor, Testing Semiconductor Memories: Theory and Practice, ComTex Publishing, 1998.
[25] A.J. van de Goor, S. Hamdioui, and Z. Al-ars, “Tests for Address Decoder Faults in RAMs Due to Inter-Gate Opens,” Proc. European Test Symp., pp. 146-151, 2004.
[26] A.J. van de Goor, S. Hamdioui, and R. Wadsworth, “Detecting Faults in the Peripheral Circuits and Evaluation on SRAM Tests,” Proc. IEEE Int'l Test Conf., pp. 114-123, 2004.

Index Terms:
Memory testing, open defects, address decoder delay faults, addressing methods, BIST, DFT.
Citation:
Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, "Opens and Delay Faults in CMOS RAM Address Decoders," IEEE Transactions on Computers, vol. 55, no. 12, pp. 1630-1639, Dec. 2006, doi:10.1109/TC.2006.203
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