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Opens and Delay Faults in CMOS RAM Address Decoders
December 2006 (vol. 55 no. 12)
pp. 1630-1639
This paper presents a complete electrical analysis of Address decoder Delay Faults "ADFs” caused by resistive opens in RAMs. A classification between inter and intragate opens is made. A systematic way is introduced to explore the space of possible tests to detect these faults; it is based on generating appropriate sensitizing address transitions and the corresponding sensitizing operation sequences. DFT features are given to facilitate the BIST implementation of the new tests.

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Index Terms:
Memory testing, open defects, address decoder delay faults, addressing methods, BIST, DFT.
Citation:
Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, "Opens and Delay Faults in CMOS RAM Address Decoders," IEEE Transactions on Computers, vol. 55, no. 12, pp. 1630-1639, Dec. 2006, doi:10.1109/TC.2006.203
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