This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition
December 2006 (vol. 55 no. 12)
pp. 1523-1535
Logarithmic number systems (LNS) offer a viable alternative in terms of area, delay, and power to binary number systems for implementing multiplication and division operations for applications in signal processing. The Mitchell algorithm (MA), proposed in [15], reduces the complexity of finding the logarithms and the antilogarithms using piecewise straight line approximations of the logarithm and the antilogarithm curves. The approximations, however, result in some loss of accuracy. Thus, several methods have been proposed in the literature for improving the accuracy of Mitchell's algorithm. In this work, we investigate a new method based on Operand Decomposition (OD) to improve the accuracy of Mitchell's algorithm when applied to logarithmic multiplication. In the OD technique proposed in [9] for reducing the amount of switching activity in binary multiplication, the two inputs to be multiplied are together decomposed into four binary operands and the product is expressed as the sum of the products of the decomposed numbers. We show that applying operand decomposition to the inputs as a preprocessing step to Mitchell's multiplication algorithm significantly improves the accuracy. Experimental results indicate that the proposed algorithm for logarithmic multiplication reduces the error percentage of Mitchell's algorithm by 44.7 percent on the average. It is also shown that the OD method yields further improvement when combined with the other correction methods proposed in the literature.

[1] K.H. Abed and R. Siferd, “CMOS VLSI Implementation of a Low-Power Logarithmic Converter,” IEEE Trans. Computers, vol. 52, no. 11, pp. 1421-1433, Nov. 2003.
[2] K.H. Abed and R. Siferd, “VLSI Implementation of a Low-Power Antilogarithmic Converter,” IEEE Trans. Computers, vol. 52, no. 9, pp. 1221-1228, Sept. 2003.
[3] M. Arnold, T. Bailey, and J. Cowles, “Error Analysis of the Kmetz/Maenner Algorithm,” J. VLSI Signal Processing, pp. 37-53, 2003.
[4] M.G. Arnold and C. Walter, “Unrestricted Faithful Rounding Is Good Enough for Some LNS Applications,” Proc. IEEE Symp. Computer Arithmetic, pp. 56-58, 2001.
[5] T.A. Brubaker and J.C. Becker, “Multiplication Using Logarithms Implemented with Read-Only-Memory,” IEEE Trans. Computers, pp. 761-766, 1975.
[6] M. Combet, H. Zonneveld, and L. Verbeek, “Computation of the Base Two Logarithm of Binary Numbers,” IEEE Trans. Electronic Computers, pp. 863-867, Dec. 1965.
[7] M.J. Duncan, “Improved Mitchell Based Logarithmic Multiplier for Low Power DSP Applications,” IEEE Int'l System on a Chip Conf. (SOCC), pp. 17-20, 2003.
[8] E.L. Hall, D.D. Lynch, and S.J. Dwyer III, “Generation of Products and Quotients Using Approximate Binary Logarithms for Digital Filtering Applications,” IEEE Trans. Computers, vol. 19, no. 2, pp.97-105, Feb. 1970.
[9] M. Ito, D. Chinnery, and K. Keutzer, “Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition,” Proc. IEEE Int'l Conf. Computer Design (ICCD), 2003.
[10] N.G. Kingsbury and P.J.W. Rayner, “Digital Filtering Using Logarithmic Arithmetic,” IEEE Electronic Letters, pp. 56-58, Jan. 1971.
[11] G.L. Kmetz, “Floating Point Logarithmic Conversion System,” United States Patent no. 4,583,180, Apr. 1986.
[12] F.S. Lai and C.F.E. Wu, “A Hybrid Number System Processor with Geometric and Complex Arithmetic Capabilities,” IEEE Trans. Computers, vol. 40, no. 8, pp. 652-662, Aug. 1991.
[13] D.M. Lewis, “Interleaved Memory Function Interpolators With Application to Accurate LNS Arithmetic Unit,” IEEE Trans. Computers, vol. 43, no. 8, pp. 974-982, Aug. 1994.
[14] R. Maenner, “A Fast Integer Binary Logarithm for Large Arguments,” IEEE Micro, pp. 41-45, Dec. 1987.
[15] J.N. Mitchell, “Computer Multiplication and Division using Binary Logarithms,” IRE Trans. Electronic Computers, pp. 512-517, vol. 11, Aug. 1962.
[16] R. Muscedere, “Difficult Operations in the Multidimensional Logarithmic Number System,” PhD thesis, Univ. of Windsor, 2003.
[17] R. Muscedere, V. Dimitrov, G.A. Jullien, and C.W. Miller, “Efficient Techniques for Binary-to-Multidigit Multidimensional Logarithmic Number System Conversion Using Range-Addressable Look-Up Tables,” IEEE Trans. Computers, vol. 54, no. 3, pp.257-272, Mar. 2005.
[18] V. Paliouras and T. Stouraitis, “Logarithm Number System for Low Power Arithmetic,” Proc. Int'l Workshop Power and Timing Modeling Optimization and Simulation, pp. 285-294, 2000.
[19] S.L. SanGregory, R.E. Siferd, C. Brother, and D. Gallagher, “Low-Power Logarithm Approximation with CMOS VLSI Implementation,” Proc. IEEE Midwest Symp. Circuits and Systems, Aug. 1999.
[20] E.E. Swartzlander, “Sign/Logarithm Arithmetic for FFT Implementation,” IEEE Trans. Computers, vol. 32, pp. 526-534, 1983.
[21] E.E. Swartzlander, “The Sign/Logarithm Number System,” IEEE Trans. Computers, vol. 24, no. 12, pp. 1238-1242, Dec. 1975.
[22] F.J. Taylor, R. Gill, and J. Joseph, “A 20 Bit Logarithmic Number System Processor,” IEEE Trans. Computers, vol. 37, no. 2, pp. 190-200, Feb. 1988.
[23] “Hypermedia Image Processing Reference,” http://www.cee. hw.ac.uk/hiprgsmooth.html , Heriot Watt Univ., Edinburgh, 1994.

Index Terms:
Computer arithmetic, error analysis, logarithmic number system, interpolation.
Citation:
V. Mahalingam, Nagarajan Ranganathan, "Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition," IEEE Transactions on Computers, vol. 55, no. 12, pp. 1523-1535, Dec. 2006, doi:10.1109/TC.2006.198
Usage of this product signifies your acceptance of the Terms of Use.