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A Simple High-Speed Multiplier Design
October 2006 (vol. 55 no. 10)
pp. 1253-1258
ASCII Text
x 
 
Jung-Yup Kang, Jean-Luc Gaudiot, "A Simple High-Speed Multiplier Design," IEEE Transactions on Computers, vol. 55, no. 10, pp. 1253-1258, October, 2006.
 
 
BibTex
x
 
@article{ 10.1109/TC.2006.156,
author = {Jung-Yup Kang and Jean-Luc Gaudiot},
title = {A Simple High-Speed Multiplier Design},
journal ={IEEE Transactions on Computers},
volume = {55},
number = {10},
issn = {0018-9340},
year = {2006},
pages = {1253-1258},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2006.156},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - A Simple High-Speed Multiplier Design
IS - 10
SN - 0018-9340
SP1253
EP1258
EPD - 1253-1258
A1 - Jung-Yup Kang,
A1 - Jean-Luc Gaudiot,
PY - 2006
KW - Multiplier
KW - Booth
KW - modified Booth
KW - partial products.
VL - 55
JA - IEEE Transactions on Computers
ER -
 
The performance of multiplication is crucial for multimedia applications such as 3D graphics and signal processing systems, which depend on the execution of large numbers of multiplications. Previously reported algorithms mainly focused on rapidly reducing the partial products rows down to final sums and carries used for the final accumulation. These techniques mostly rely on circuit optimization and minimization of the critical paths. In this paper, an algorithm to achieve fast multiplication in two's complement representation is presented. Rather than focusing on reducing the partial products rows down to final sums and carries, our approach strives to generate fewer partial products rows. In turn, this influences the speed of the multiplication, even before applying partial products reduction techniques. Fewer partial products rows are produced, thereby lowering the overall operation time. In addition to the speed improvement, our algorithm results in a true diamond-shape for the partial product tree, which is more efficient in terms of implementation. The synthesis results of our multiplication algorithm using the Artisan TSMC 0.13um 1.2-Volt standard-cell library show 13 percent improvement in speed and 14 percent improvement in power savings for 8-bit \times 8-bit multiplications (10 percent and 3 percent, respectively, for 16-bit \times 16-bit multiplications) when compared to conventional multiplication algorithms.

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Index Terms:
Multiplier, Booth, modified Booth, partial products.
Citation:
Jung-Yup Kang, Jean-Luc Gaudiot, "A Simple High-Speed Multiplier Design," IEEE Transactions on Computers, vol. 55, no. 10, pp. 1253-1258, Oct. 2006, doi:10.1109/TC.2006.156
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