This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Truncated Online Arithmetic with Applications to Communication Systems
October 2006 (vol. 55 no. 10)
pp. 1240-12529
Truncation in digit-precision is a very important and common operation in embedded system design for bounding the required finite precision and for area-time-power savings. In this paper, we present the use of online arithmetic to provide truncated computations with communication systems as one of the applications. In contrast to truncation in conventional arithmetic, online arithmetic can truncate dynamically and produce both area and time benefits due to the digit-serial nature of computations. This is of great advantage in communication systems where the precision requirements can change dynamically with the environment. While truncation in conventional arithmetic can have significant truncation errors, especially when the output precision is less than the input precision, the redundancy and most significant digit first nature of online arithmetic restricts the truncation error to only the least significant digit of the truncated result. As an application that uses significant truncation in precision, a code matched filter detector for wireless systems is designed using truncated online arithmetic. The detector can provide both hard decisions and soft(er) decisions dynamically as well as interface with other conventional arithmetic circuits or act as a DSP coprocessor. Thus, optimized communication receivers with coexisting conventional arithmetic for saturation and online arithmetic for truncation can now be built. The truncated online arithmetic detector was also verified with a VLSI implementation in an AMI 0.5 \mu MOSIS tiny chip process.

[1] M.J. Schulte and E.E. Swartzlander, “Truncated Multiplication with Correction Constant,” Proc. Workshop VLSI Signal Processing, vol. VI, pp. 388-396, Oct. 1993.
[2] P.I. Balzola, M.J. Schulte, J. Ruan, J. Glossner, and E. Hokenek, “Design Alternatives for Parallel Saturating Multioperand Adders,” Proc. IEEE Int'l Conf. Computer Design (ICCD), pp. 172-177, 2001.
[3] M.J. Schulte, J.E. Stine, and J.G. Jansen, “Reduced Power Dissipation through Truncated Multiplication,” Proc. IEEE Alessandro Volta Memorial Workshop Low Power Design, pp. 61-69, Mar. 1999
[4] Z. Huang and M.D. Ercegovac, “Two-Dimensional Signal Gating for Low-Power Array Multiplier Design,” Proc. IEEE Int'l Conf. Circuits and Systems, vol. 1, pp. 489-492, May 2002.
[5] K.E. Wires, M.J. Schulte, and J.E. Stine, “Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation,” Proc. IEEE Int'l Conf. Computer Design (ICCD), pp. 497-500, Sept. 2001.
[6] M.D. Ercegovac, “Online Arithmetic: An Overview,” Proc. Real Time Signal Processing VII, SPIE, pp. 86-93, Aug. 1984.
[7] E.G. Walters and M.J. Schulte, “Design Tradeoffs Using Truncated Multipliers in FIR Filter Implementations,” Proc. SPIE: Advanced Signal Processing Algorithms, Architectures, and Implementations, July 2002.
[8] S. Oraintara, Y.J. Chen, and T.Q. Nguyen, “Integer Fast Fourier Transform,” IEEE Trans. Signal Processing, vol. 50, no. 3, pp. 607-618, Mar. 2002.
[9] J. Markel and A. Gray Jr., “Fixed-Point Truncation Arithmetic Implementation of a Linear Prediction Autocorrelation Vocoder,” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 22, no. 4, pp. 273-282, Aug. 1974.
[10] S. Rajagopal, S. Bhashyam, J.R. Cavallaro, and B. Aazhang, “Real-Time Algorithms and Architectures for Multiuser Channel Estimation and Detection in Wireless Base-Station Receivers,” IEEE Trans. Wireless Comm., vol. 1, no. 3, pp. 468-479, July 2002.
[11] M.D. Ercegovac and T. Lang, “Online Arithmetic: A Design Methodology and Applications in Digital Signal Processing,” Proc. VLSI Signal Processing III, pp. 252-263, Nov. 1988.
[12] J. Bruguera and T. Lang, “2-D DCT Using Online Arithmetic,” Proc. Int'l Conf. Acoustics, Speech, and Signal Processing (ICASSP), vol. 5, pp. 3275-3278, May 1995.
[13] S. Rajagopal and J.R. Cavallaro, “Online Arithmetic for Detection in Digital Communication Receivers,” Proc. 15th IEEE Int'l Symp. Computer Arithmetic (ARITH-15), pp. 257-265, June 2001.
[14] T. Lynch and M.J. Schulte, “A High Radix Online Arithmetic for Credible and Accurate Computing,” J. Universal Computer Science, vol. 1, no. 7, pp. 439-453, July 1995.
[15] R. McIlhenny and M.D. Ercegovac, “Online Algorithms for Complex Number Arithmetic,” 32nd Asilomar Conf. Signals, Systems, and Computers, pp. 172-176, Oct. 1998.
[16] N.D. Hemkumar and J.R. Cavallaro, “Redundant and Online CORDIC for Unitary Transformations,” IEEE Trans. Computers, special issue on computer arithmetic, vol. 43, no. 8, pp. 941-954, Aug. 1994.
[17] M.D. Ercegovac and A.L. Grnarov, “On the Performance of Online Arithmetic,” Proc. Int'l Conf. Parallel Processing, pp. 55-62, Aug. 1980.
[18] M.D. Ercegovac and T. Lang, “On-the-Fly Conversion of Redundant into Conventional Representations,” IEEE Trans. Computers, vol. 36, no. 7, pp. 895-897, July 1987.
[19] A. Avizienis, “Signed-Digit Number Representations for Fast Parallel Arithmetic,” IRE Trans. Electronic Computers, vol. 10, no. 3, pp. 389-400, Sept. 1961.
[20] S. Moshavi, “Multi-User Detection for DS-CDMA Communications,” IEEE Comm. Magazine, pp. 124-136, Oct. 1996.
[21] S. Verdú, Multiuser Detection. Cambridge Univ. Press, 1998.
[22] M. Honig, U. Madhow, and S. Verdú, “Blind Adaptive Multiuser Detection,” IEEE Trans. Information Theory, vol. 41, no. 4, pp. 944-960, July 1995.
[23] J. Chen, G. Shou, and C. Zhou, “High-Speed Low-Power Complex Matched Filter for W-CDMA: Algorithm and VLSI Architecture,” IEICE Trans. Fundamentals, vol. E83-A, no. 1, pp. 150-157, Jan. 2000.
[24] K. Chapman, P. Hardy, A. Miller, and M. George, “CDMA Matched Filter Implementation in Virtex Devices,” Xilinx Application Note XAPP212(v1. 1), Jan. 2001.
[25] T. Long and N.R. Shanbhag, “Low-Power CDMA Multiuser Receiver Architectures,” Proc. IEEE Workshop Signal Processing Systems, pp. 493-502, Oct. 1999.
[26] R.H. Walden, “Performance Trends in Analog-to-Digital Converters,” IEEE Comm. Magazine, vol. 37, no. 2, pp. 96-101, Feb. 1999.
[27] I. Seskar and N.B. Mandayam, “A Software Radio Architecture for Linear Multiuser Detection,” IEEE J. Selected Areas in Comm., vol. 17, no. 5, pp. 814-823, May 1999.
[28] N. Zhang, A. Poon, D. Tse, R. Brodersen, and S. Verdú, “Trade-Offs of Performance and Single Chip Implementation of Indoor Wireless Multi-Access Receivers,” Proc. IEEE Wireless Comm. and Networking Conf. (WCNC), vol. 1, pp. 226-230, Sept. 1999.
[29] B. Parhami, Computer Arithmetic— Algorithms and Hardware Designs. Oxford Univ. Press, 2000.
[30] S. Waser and M.J. Flynn, Introduction to Arithmetic for Digital System Designers. CBS College Publishing, 1982.
[31] I. Koren, Computer Arithmetic Algorithms. Prentice Hall, 1993.
[32] J.G. Proakis and M. Salehi, Communication Systems Engineering. Prentice Hall, 1994.
[33] A. Gorji-Sinaki and M.D. Ercegovac, “Design of a Digit-Slice Online Arithmetic Unit,” Proc. Fifth IEEE Symp. Computer Arithmetic, pp. 72-80, May 1981.
[34] J.S. Fernando and M.D. Ercegovac, “Conventional and Online Arithmetic Designs for High-Speed Recursive Digital Filters,” Proc. Fifth IEEE Workshop VLSI Signal Processing, pp. 81-90, Oct. 1992.
[35] M.D. Ercegovac, “A General Hardware-Oriented Method for Evaluation of Functions and Computations in a Digital Computer,” IEEE Trans. Computers, vol. 26, no. 7, pp. 667-680, July 1977.
[36] A. Guyot, Y. Herreros, and J-M. Muller, “JANUS: An Online Multiplier/Divider for Manipulating Large Numbers,” Proc. Ninth IEEE Symp. Computer Arithmetic, pp. 106-111, Sept. 1989.
[37] A.F. Tenca, M.D. Ercegovac, and M.E. Louie, “Fast Online Multiplication Units Using LSA Organization,” Proc. Advanced Signal Processing Algorithms, Architectures, and Implementations IX, SPIE, pp. 74-83, July 1999.
[38] C.R. Baugh and B.A. Wooley, “A Two's Complement Parallel Array Multiplication Algorithm,” IEEE Trans. Computers, vol. 22, no. 12, pp. 1045-1047, Dec. 1973.
[39] K'A.C. Bickerstaff, E.E. Swartzlander, and M.J. Schulte, “Analysis of Column Compression Multipliers,” Proc. IEEE Int'l Symp. Computer Arithmetic, pp. 33-39, June 2001.
[40] G. Wang and M. Tull, “The Implementation of an Efficient and High-Speed Inner-Product Processor,” Proc. 35th Asilomar Conf. Signals, Systems, and Computers, vol. 2, pp. 1362-1366, Oct. 2001.
[41] N. Azakova, R. Sung, N. Durdle, M. Margala, and J. Lamoureux, “Fast and Low-Power Inner Product Processor,” Proc. 2001 IEEE Int'l Symp. Circuits and Systems (ISCAS), vol. 4, pp. 646-649, May 2001.
[42] P. Radosavljevic, M. Gadhiok, and N. Bagge, “Online Arithmetic Matched Filter Detector,” Dec. 2002.
[43] C. Cook, N. Deneau, R. Dubey, and A. Lin, “Conventional Arithmetic Matched Filter Detector,” Dec. 2002.
[44] “VLSI Signal Processing Research at Rice University,” http://www.ece.rice.edu/~cavallarvlsi, 2006.

Index Terms:
Dynamic truncation, finite precision, online arithmetic, communication systems.
Citation:
Sridhar Rajagopal, Joseph R. Cavallaro, "Truncated Online Arithmetic with Applications to Communication Systems," IEEE Transactions on Computers, vol. 55, no. 10, pp. 1240-12529, Oct. 2006, doi:10.1109/TC.2006.168
Usage of this product signifies your acceptance of the Terms of Use.