Tamper Proofing by Design Using Generalized Involution-Based Concurrent Error Detection for Involutional Substitution Permutation and Feistel Networks
Issue No.10 - October (2006 vol.55)
Nikhil Joshi , IEEE
Kaijie Wu , IEEE
Bo Yang , IEEE
Ramesh Karri , IEEE
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2006.167
Secure operation of cryptographic algorithms is critical to the success of secure transactions. Fault-based attacks that recover secret keys by deliberately introducing fault(s) in cipher implementations and analyzing the faulty outputs have been proven to be extremely powerful. Substitution Permutation Networks (SPN) and Feistel Networks (FN) are the two important classes of Symmetric Block Ciphers. Some SPN ciphers and all FN Ciphers satisfy the involution property. A function F is an involution if F(F(x)) = x. In this paper, we investigate tamper proofing techniques that use low cost involution-based time redundancy concurrent error detection (CED) schemes for involutional SPN and FN symmetric block ciphers. We incorporated this tamper proofing by design technique in a hardware implementation of the 128-bit ANUBIS SPN cipher (an involution variant of the Advanced Encryption Standard (AES)) and the 128-bit TwoFish FN cipher (an AES finalist). We performed fault simulation at both the algorithm and the gate level to show that the low-cost involution-based CED schemes, in addition to detecting all transient faults, can detect all single-bit permanent faults and > 99 percent of all multiple-bit permanent faults. Consequently, this low cost CED technique can protect the crypto device against Differential Fault Analysis (DFA) attacks.
Concurrent Error Detection (CED), tamper proofing, Subsitution Permutation Networks (SPN), Feistel networks, cryptography, ANUBIS, TwoFish.
Nikhil Joshi, Jayachandran Sundararajan, Kaijie Wu, Bo Yang, Ramesh Karri, "Tamper Proofing by Design Using Generalized Involution-Based Concurrent Error Detection for Involutional Substitution Permutation and Feistel Networks", IEEE Transactions on Computers, vol.55, no. 10, pp. 1230-1239, October 2006, doi:10.1109/TC.2006.167