Issue No.09 - September (2006 vol.55)
Maciej Ciesielski , IEEE
Priyank Kalla , IEEE
Serkan Askar , IEEE
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2006.153
A Taylor Expansion Diagram (TED) is a compact, word-level, canonical representation for data flow computations that can be expressed as multivariate polynomials. TEDs are based on a decomposition scheme using Taylor series expansion that allows one to model word-level signals as algebraic symbols. This power of abstraction, combined with the canonicity and compactness of TED, makes it applicable to equivalence verification of dataflow designs. The paper describes the theory of TEDs and proves their canonicity. It shows how to construct a TED from an HDL design specification and discusses the application of TEDs in proving the equivalence of such designs. Experiments were performed with a variety of designs to observe the potential and limitations of TEDs for dataflow design verification. Application of TEDs to algorithmic and behavioral verification is demonstrated.
Register transfer level—design aids, verification; arithmetic and logic structures—verification; symbolic and algebraic manipulation.
Maciej Ciesielski, Priyank Kalla, Serkan Askar, "Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs", IEEE Transactions on Computers, vol.55, no. 9, pp. 1188-1201, September 2006, doi:10.1109/TC.2006.153