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Throttling-Based Resource Management in High Performance Multithreaded Architectures
September 2006 (vol. 55 no. 9)
pp. 1142-1152
Up to now, the power problems which could be caused by the huge amount of hardware resources present in modern systems have not been a primary concern. More recently, however, power consumption has begun limiting the number of resources which can be safely integrated into a single package, lest the heat dissipation exceed physical limits (before actual package meltdown). At the same time, new architectural techniques such as Simultaneous MultiThreading (SMT), whose goal it is to efficiently use the resources of a superscalar machine without introducing excessive additional control overhead, have appeared on the scene. In this paper, we present a new resource management scheme which enables an efficient low power mode in SMT architectures. The proposed scheme is based on a modified pipeline throttling technique which introduces a throttling point at the last stage of the processor pipeline in order to reduce power consumption. We demonstrate that resource utilization plays an important role in efficient power management and that our strategy can significantly improve performance in the power-saving mode. Since the proposed resource management scheme tests the processor condition cycle by cycle, we evaluate its performance by setting a target IPC as one sort of immediate power measure. Our analysis shows that an SMT processor with our dynamic resource management scheme can yield significantly higher overall performance.

[1] S. Eggers, J. Emer, H. Levy, J. Lo, R. Stamm, and D. Tullsen, “Simultaneous Multithreading: A Platform for Next-Generation Processors,” IEEE Micro, pp. 12-18, Sept./Oct. 1997.
[2] L. Hammond, B. Nayfeh, and K. Olukotun, “A Single-Chip Multiprocessor,” Computer, special issue on billion-transistor processors, vol. 30, no. 9, pp. 79-85, Sept. 1997.
[3] J. Lo, S. Eggers, J. Emer, H. Levy, R. Stamm, and D. Tullsen, “Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading,” ACM Trans. Computer Systems, pp. 322-354, Aug. 1997.
[4] Intel Pentium 4 Processor Datasheet, Intel Corp., 2002.
[5] Intel Pentium 4 Processor Thermal Design Guidelines, Intel Corp., 2000.
[6] T. Mudge, “Power: A First Class Design Constraint for Future Architectures,” Proc. Seventh Int'l Conf. High Performance Computing, pp. 215-224, Dec. 2000.
[7] J. Seng, D. Tullsen, and G. Cai, “Power-Sensitive Multithreaded Architecture,” Proc. 2000 Int'l Conf. Computer Design, pp. 119-206, Sept. 2000.
[8] PowerPC: MPC750 RISC Microprocessor Technical Summary, Motorola Inc., 1997.
[9] H. Sanchez, B. Kuttanna, T. Olson, M. Alexander, G. Gerosa, R. Philip, and J. Alvarez, “Thermal Management System for High Performance PowerPC Microprocessors,” Proc. 42nd IEEE Int'l Computer Conf., pp. 325-330, Feb. 1997.
[10] S. Manne, A. Klauser, and D. Grunwald, “Pipeline Gating: Speculation Control for Energy Reduction,” Proc. 25th Ann. Int'l Symp. Computer Architecture, pp. 132-141, June 1998.
[11] D. Tullsen, S. Eggers, and H. Levy, “Simultaneous Multithreading: Maximizing On-Chip Parallelism,” Proc. 22nd Ann. Int'l Symp. Computer Architecture, pp. 392-403, June 1995.
[12] D. Tullsen, S. Eggers, J. Emer, H. Levy, J. Lo, and R. Stamm, “Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor,” Proc. 23rd Ann. Int'l Symp. Computer Architecture, pp. 191-202, May 1996.
[13] N. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. Hu, M. Irwin, M. Kandemir, and V. Narayanan, “Leakage Current: Moore's Law Meets Static Power,” Computer, vol. 36, no. 12, pp.65-77, Dec. 2003.
[14] R. Gonzalez, B. Gordon, and M. Horowitz, “Supply and Threshold Voltage Scaling for Low Power CMOS,” IEEE J. Solid-State Circuits, vol. 32, no. 8, pp. 1210-1216, Aug. 1997.
[15] C. Chuang, P. Lu, and C. Anderson, “SOI for Digital CMOS VLSI: Design Considerations and Advances,” Proc. IEEE, vol. 86, no. 4, pp. 689-720, Apr. 1998.
[16] J. Kao and A. Chandrakasan, “Dual-Threshold Voltage Techniques for Low-Power Digital Circuits,” IEEE J. Solid-State Circuits, no.7, pp. 1009-1018, July 2000.
[17] M. Flynn, P. Hung, and K. Rudd, “Deep-Submicron Microprocessor Design Issues,” IEEE Micro, vol. 19, no. 4, pp. 11-22, July/Aug. 1999.
[18] R. Gonzalez and M. Horowitz, “Energy Dissipation in General Purpose Microprocessors,” IEEE J. Solid-State Circuits, vol. 21, no. 9, pp. 1277-1284, Sept. 1996.
[19] J. Brennan, A. Dean, S. Kenyon, and S. Ventrone, “Low Power Methodology and Design Techniques for Processor Design,” Proc. 1998 Int'l Symp. Low-Power Electronics and Design, pp. 268-273, Aug. 1998.
[20] S. Lee and J.-L. Gaudiot, “Clustered Microarchitecture Simultaneous Multithreading,” Proc. Parallel Processing, Ninth Int'l Euro-Par Conf. (Euro-Par 2003), H. Kosch, L. Böszörményi, and H.Hellwagner, eds., pp. 576-585, Aug. 2003.
[21] M. Gowan, L. Biro, and D. Jackson, “Power Considerations in the Design of the Alpha 21264 Microprocessor,” Proc. 35th Design Automation Conf., pp. 726-731, June 1998.
[22] T. Burd, T. Pering, A. Stratakos, and R. Brodersen, “A Dynamic Voltage Scaled Microprocessor System,” IEEE J. Solid-State Circuits, pp. 1571-1580, Nov. 2000.
[23] N. Kim and T. Mudge, “Reducing Register Ports Using Delayed Write-Back Queues and Operand Pre-Fetch,” Proc. 17th Ann. Int'l Conf. Supercomputing, pp. 172-182, June 2003.
[24] G. Savransky, R. Ronen, and A. Gonzalez, “Lazy Retirement: A Power Aware Register Management Mechanism,” Proc. Workshop Complexity-Effective Design, 29th Int'l Symp. Computer Architecture, May 2002.
[25] J.-L. Cruz, A. Gonzalez, M. Valero, and N. Topham, “Multiple-Banked Register File Architectures,” Proc. 27th Ann. Int'l Symp. Computer Architecture, pp. 316-325, June 2000.
[26] S. Lee and J.-L. Gaudiot, “ALPSS: Architectural Level Power Simulator for Simultaneous Multithreading, Version 1.0,” Technical Report CENG-02-04, Univ. of Southern California, Apr. 2002.
[27] T. Austin, “The SimpleScalar Architectural Research Tool Set, Version 2. 0,” Technical Report 1342, Univ. of Wisconsin-Madison, June 1997.
[28] D. Brooks, V. Tiwari, and M. Martonosi, “Wattch: A Framework for Architectural-Level Power Analysis and Optimizations,” Proc. 27th Ann. Int'l Symp. Computer Architecture, pp. 83-94, June 2000.
[29] G. Cai and C.-H. Lim, “Architectural Level Power/Performance Optimization and Dynamic Power Estimation,” Cool Chips Tutorial colocated with MICRO32, Nov. 1999.
[30] J. Henning, “SPEC CPU2000: Measuring CPU Performance in the New Millennium,” Computer, vol. 33, no. 7, pp. 28-35, July 2000.
[31] Alpha 21264 Microprocessor Hardware Reference Manual, Compaq Computer Corp., 1999.
[32] R. Preston, R. Badeau, D. Bailey, S. Bell, L. Biro, W. Bowhill, D. Dever, S. Felix, R. Gammack, V. Germini, M. Gowan, P. Gronowski, D. Jackson, S. Mehta, S. Morton, J. Pickholtz, M. Reilly, and M. Smith, “Design of an 8-Wide Superscalar RISC Microprocessor with Simultaneous Multithreading,” Digest of Technical Papers, 2002 IEEE Int'l Solid-State Circuits Conf., pp. 334-335, Feb. 2002.
[33] S. McFarling, “Combining Branch Predictors,” Technical Report WRL-TN-36, Western Research Laboratory, Digital June 1993.
[34] R. Kessler, “The Alpha 21264 Microprocessor,” IEEE Micro, vol. 19, no. 2, pp. 24-36, Mar./Apr. 1999.
[35] D. Brooks and M. Martonosi, “Dynamic Thermal Management for High-Performance Microprocessors,” Proc. Seventh Int'l Symp. High Performance Computer Architecture, pp. 171-182, Jan. 2001.
[36] C. Shin, S. Lee, and J.-L. Gaudiot, “Dynamic Scheduling Issues in SMT Architectures,” Proc. 17th Int'l Parallel and Distributed Processing Symp. (IPDPS '03), Apr. 2003.

Index Terms:
Resource management, power management, multithreading, throttling, resource utilization.
Citation:
Seong-Won Lee, Jean-Luc Gaudiot, "Throttling-Based Resource Management in High Performance Multithreaded Architectures," IEEE Transactions on Computers, vol. 55, no. 9, pp. 1142-1152, Sept. 2006, doi:10.1109/TC.2006.154
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