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Fault Detection Architectures for Field Multiplication Using Polynomial Bases
September 2006 (vol. 55 no. 9)
pp. 1089-1103
In many cryptographic schemes, the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation for bit parallel operation may require millions of logic gates. Some of these gates may become faulty in the field due to natural causes or malicious attacks, which may lead to the generation of erroneous outputs by the multiplier. In this paper, we propose new architectures to detect erroneous outputs caused by certain types of faults in bit-parallel and bit-serial polynomial basis multipliers over finite fields of characteristic two. In particular, parity prediction schemes are developed for detecting errors due to single and certain multiple stuck-at faults. Although the issue of detecting soft errors in registers is not considered, the proposed schemes have the advantage that they can be used with any irreducible binary polynomial chosen to define the finite field.

[1] G.B. Agnew, T. Beth, R.C. Mullin, and S.A. Vanstone, “Arithmetic Operations in $GF(2^m)$ ,” J. Cryptology, vol. 6, pp. 3-13, 1993.
[2] G. Bertoni, L. Breveglieri, I. Koren, P. Maistri, and V. Piuri, “Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard,” IEEE Trans. Computers, special issue on cryptographic hardware and embedded systems, vol. 52, no. 4, pp. 492-505, Apr. 2003.
[3] D. Boneh, R.A. DeMillo, and R.J. Lipton, “On the Importance of Eliminating Errors in Cryptographic Computations,” J. Cryptology, vol. 14, pp. 101-119, 2001.
[4] M. Ciet and M. Joye, “Elliptic Curve Cryptosystems in the Presence of Permanent and Transient Faults,” Designs, Codes, and Cryptography, vol. 36, no. 1, pp. 33-43, 2005.
[5] S. Fenn, M. Gossel, M. Benaissa, and D. Taylor, “On-Line Error Detection for Bit-Serial Multipliers in $GF(2^m)$ ,” J. Electronic Testing: Theory and Applications, vol. 13, pp. 29-40, 1998.
[6] A. Halbutogullari and Ç.K. Koç, “Mastrovito Multiplier for General Irreducible Polynomials,” IEEE Trans. Computers, vol. 49, no. 5, pp. 503-518, May 2000.
[7] B.W. Johnson, Design and Analysis of Fault-Tolerant Digital Systems. Addison-Wesley, 1989.
[8] M. Joye, A.K. Lenstra, and J.J. Quisquater, “Chinese Remaindering Based Cryptosystems in the Presence of Faults,” J. Cryptology, vol. 12, pp. 241-245, 1999.
[9] E.D. Mastrovito, “VLSI Designs for Multiplication over Finite Fields $GF(2^m)$ ,” Proc. Symp. Applied Algebra, Algebraic Algorithms, and Error Correcting Codes (AAECC-6), pp. 297-309, July 1988.
[10] E.D. Mastrovito, “VLSI Architectures for Computation in Galois Fields,” PhD thesis, Linkoping Univ., Linkoping, Sweden, 1991.
[11] M. Nicolaidis, R.O. Duarte, S. Manich, and J. Figueras, “Fault-Secure Parity Prediction Arithmetic Operators,” IEEE Design and Test of Computers, pp. 60-71, Apr.-June 1997.
[12] C. Paar, P. Fleishmann, and P. Soria-Rodriguez, “Fast Arithmetic for Public-Key Algorithms in Galois Fields with Composite Exponents,” IEEE Trans. Computers, vol. 48, no. 10, pp. 1025-1034, Oct. 1999.
[13] A. Reyhani-Masoleh and M.A. Hasan, “Error Detection in Polynomial Basis Multipliers over Binary Extension Fields,” Proc. Workshop Cryptographic Hardware and Embedded Systems (CHES 2002), pp. 515-528, Aug. 2002.
[14] A. Reyhani-Masoleh and M.A. Hasan, “Low Complexity Bit Parallel Architectures for Polynomial Basis Multiplication over $GF(2^m)$ ,” IEEE Trans. Computers, vol. 53, no. 8, pp. 945-959, Aug. 2004.
[15] F. Rodriguez-Henriquez and Ç.K. Koç, “Parallel Multipliers Based on Special Irreducible Pentanomials,” IEEE Trans. Computers, vol. 52, no. 12, pp. 1535-1542, Dec. 2003.
[16] G. Seroussi, “Table of Low-Weight Binary Irreducible Polynomials,” HP Labs Technical Report HPL-98-135, Aug. 1998.
[17] H. Wu, “Bit-Parallel Finite Field Multiplier and Squarer Using Polynomial Basis,” IEEE Trans. Computers, vol. 51, no. 7, pp. 750-758, July 2002.
[18] H. Wu and M.A. Hasan, “Efficient Exponentiation of a Primitive Root in $GF(2^m)$ ,” IEEE Trans. Computers, vol. 46, no. 2, pp. 162-172, Feb. 1997.
[19] K. Wu, R. Karri, G. Kuznetsov, and M. Goessel, “Low Cost Concurrent Error Detection for the Advanced Encryption Standard,” Proc. IEEE Int'l Test Conf. (ITC 2004), pp. 1242-1248, 2004.
[20] T. Zhang and K.K. Parhi, “Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials,” IEEE Trans. Computers, vol. 50, no. 7, pp. 734-748, July 2001.

Index Terms:
Finite fields, polynomial basis multiplier, error detection.
Citation:
Arash Reyhani-Masoleh, M. Anwar Hasan, "Fault Detection Architectures for Field Multiplication Using Polynomial Bases," IEEE Transactions on Computers, vol. 55, no. 9, pp. 1089-1103, Sept. 2006, doi:10.1109/TC.2006.147
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