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| Mustafa Gok, Michael J. Schulte, Mark G. Arnold, "Integer Multipliers with Overflow Detection," IEEE Transactions on Computers, vol. 55, no. 8, pp. 1062-1066, August, 2006. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.2006.126, author = {Mustafa Gok and Michael J. Schulte and Mark G. Arnold}, title = {Integer Multipliers with Overflow Detection}, journal ={IEEE Transactions on Computers}, volume = {55}, number = {8}, issn = {0018-9340}, year = {2006}, pages = {1062-1066}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2006.126}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Integer Multipliers with Overflow Detection IS - 8 SN - 0018-9340 SP1062 EP1066 EPD - 1062-1066 A1 - Mustafa Gok, A1 - Michael J. Schulte, A1 - Mark G. Arnold, PY - 2006 KW - Computer arithmetic KW - high-speed arithmetic algorithms KW - combinational logic KW - overflow detection KW - multiplication. VL - 55 JA - IEEE Transactions on Computers ER - | |||
[1] P. Lapsley, DSP Processor Fundamentals: Architectures and Features. IEEE Press, 1997.
[2] J.L. Hennessy and D.A. Patterson, Computer Architecture a Quantitative Approach, second ed., pp. A-11. Morgan Kaufmann, 1996.
[3] K. Guttag, “Built-In Overflow Detection Speeds 16-Bit Microprocessor Arithmetic,” EDN, vol. 28, pp. 133-135, Jan. 1983.
[4] IBM, Power PC Microprocessor Family: The Programming Environments for 32-Bit Microprocessors, no. G522-0290-01, Feb. 2000.
[5] T. Lindholm and F. Yelin, The Java Virtual Machine Specification. Addison-Wesley, 1996.
[6] E.W. Mahurin, “Method and Circuit for Detecting Overflow in Operand Multiplication,” Patent No. 6,151,616, Nov. 2000.
[7] M.J. Schulte, P.I. Balzola, A. Akkas, and R.W. Brocato, “Integer Multiplication with Overflow Detection or Saturation,” IEEE Trans. Computers, vol. 49, no. 7, pp. 681-691, July 2000.
[8] M.J. Schulte, M. Gok, P.I. Balzola, and R.W. Brocato, “Combined Unsigned and Two's Complement Saturating Multipliers,” Proc. SPIE: Advanced Signal Processing Algorithms, Architectures, and Implementations, pp. 185-196, 2000.
[9] M. Gok, M.J. Schulte, P.I. Balzola, and R.W. Brocato, “Efficient Integer Multiplication Overflow Detection Circuits,” Proc. 35th Asilomar Conf. Signals, Systems, and Computers, pp. 1661-1665, 2001.
[10] Y. Baydatch and R. Hasharon, “Overflow Detection for Integer Multiply Instruction,” Patent No. 5,801,978, Sept. 1998.
[11] Y.H. Cha, G.Y. Cho, H.H. Choi, and H.B. Song, “Bit Result Integer Multiplier with Overflow Detector,” IEE Electronic Letters, vol. 37, pp. 940-942, July 2001.
[12] M. Gok, “Integer Multiplier and Squarer Architectures with Overflow Detection,” PhD thesis, Lehigh Univ., 2003, http://www.cse.lehigh.edu/~caarpublicationpg.html .
[13] R. Zimmermann, “Binary Adder Architectures for Cell-Based VLSI and Their Synthesis,” PhD thesis, Swiss Federal Inst. of Technology, Zurich, Switzerland, 1997.
[14] R.E. Ladner and M.J. Fischer, “Parallel Prefix Computation,” J. ACM, vol. 27, pp. 831-838, Oct. 1980.
[15] J. Sklansky, “Conditional Sum Addition Logic,” IRE Trans. Electronic Computers, vol. 9, pp. 226-231, June 1960.
[16] P.M. Kogge and H.S. Stone, “A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations,” IEEE Trans. Computers, vol. 22, pp. 786-792, Aug. 1973.
[17] R.P. Brent and H.T. Kung, “A Regular Layout for Parallel Adders,” IEEE Trans. Computers, vol. 31, no. 3, pp. 260-264, Mar. 1982.