This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory
August 2006 (vol. 55 no. 8)
pp. 1011-1023
The continuous scaling trends of interconnect wires in deep submicron (DSM) circuits result in increased interconnect delay and crosstalk noise. In this work, we develop a new postlayout gate sizing algorithm for simultaneous optimization of interconnect delay and crosstalk noise. The problem of postlayout gate sizing is modeled as a normal form game and solved using Nash equilibrium. The crosstalk noise induced on a net depends on the size of its driver gate and the size of the gates driving its coupled nets. Increasing the gate size of the driver increases the noise induced by the net on its coupled nets, whereas increasing the size of the drivers of coupled nets increases the noise induced on the net itself, resulting in a cyclic order dependency leading to a conflicting situation. It is pointed out in [1] that solving the postroute gate sizing problem for crosstalk noise optimization is difficult due to its conflicting nature. Game theory provides a natural framework for handling such conflicting situations and allows optimization of multiple parameters. By utilizing this property of game theory, the cyclic dependency of crosstalk noise on its gate sizes can be solved as well as the problem of gate sizing for simultaneous optimization of interconnect delay and crosstalk noise can be effectively modeled, whose objective function is again conflicting in nature. We have implemented two different strategies in which games are ordered according to 1) the noise criticality and 2) delay criticality of nets. The time and space complexities of the proposed gate sizing algorithm are linear in terms of the number of gates in the design. Experimental results for a noise critically ordered game theoretic approach on several medium and large open core designs indicate average improvements of 15.48 percent and 18.56 percent with respect to Cadence place and route tools in terms of interconnect delay and crosstalk noise, respectively, without any area overhead or the need for rerouting. Further, the algorithm performs significantly better than simulated annealing and genetic search as established through experimental results. A mathematical proof of existence for the Nash equilibrium solution for the proposed gate sizing formulation is also provided.

[1] M.R. Becer, D. Blaauw, I. Algor, R. Panda, C. Oh, V. Zolotov, and I.N. Hajj, “PostRoute Gate Sizing for Crosstalk Noise Reduction,” Proc. Int'l Symp. Quality Electronic Design (ISQED), pp. 171-176, Mar. 2003.
[2] H.B. Bakoglu, Circuits, Interconnections and Packaging for VLSI. Addison-Wesley, 1990.
[3] ITRS, “International Technology Roadmap for Semiconductors,” http:/public.itrs.net, 2004.
[4] C. Hu, “Future CMOS Scaling and Reliability,” Proc. IEEE, vol. 81, no. 5, pp. 682-689, May 1993.
[5] K. Rahmat, O.S. Nakagawa, S.-Y. Oh, and J. Moll, “A Scaling Scheme for Interconnect in Deep Submicron Processes,” Technical Report HPL-95-77, Hewlett-Packard Laboratories, pp. 1-4, July 1995.
[6] D. Sylvester and K. Keutzer, “Getting to the Bottom of Deep Submicron,” Proc. Int'l Conf. Computer Aided Design (ICCAD), pp.203-211, Nov. 1998.
[7] J. Cong, L. He, K. Kei-Yong, K. Cheng-Ko, and D.Z. Pan, “Interconnect Design for Deep Submicron ICs,” Proc. Int'l Conf. Computer Aided Design (ICCAD), pp. 478-485, 1997.
[8] N. Shanbhag, K. Soumyanath, and S. Martin, “Reliable Low-Power Design in the Presence of Deep Submicron Noise,” Proc. Int'l Symp. Low Power Electronics and Design, pp. 295-302, 2000.
[9] K.T. Tang and E.B Friedman, “Interconnect Coupling Noise in CMOS VLSI Circuits,” Proc. Int'l Symp. Physical Design (ISPD), pp.48-53, 1999.
[10] C.C. Chang, J. Cong, D. Zhigang, and X. Yuan, “Interconnect-Driven Floorplanning with Fast Global Wiring Planning and Optimization,” Proc. SRC Techcon Conf., pp. 21-23, Sept. 2000.
[11] J. Cong and K. Cheng-Kok, “Simultaneous Driver and Wire Sizing for Performance and Power Optimization,” Proc. Int'l Conf. Computer Aided Design (ICCAD), Nov. 1994.
[12] J.I. Hui-Ru, C. Yao-Wen, and J. Jing-Yang, “Crosstalk-Driven Interconnect Optimization by Simultaneous Gate and Wire Sizing,” IEEE Trans. Computer-Aided Design, vol. 19, no. 9, pp.999-1010, Sept. 2000.
[13] C.C.N. Chu and D.F. Wong, “Closed Form Solution to Simultaneous Buffer Insertion/Sizing and Wire Sizing,” ACM Trans. Design Automation of Electronic Systems, vol. 6, no. 3, pp. 343-371, July 2001.
[14] T. Xiao and M.M. Sadowska, “Gate Sizing to Eliminate Crosstalk Induced Timing Violation,” Proc. Int'l Conf. Computer Aided Design (ICCAD), pp. 186-191, 2001.
[15] C. Alpert, C. Chu, G. Gandham, M. Hrkic, J. Hu, C. Kashyap, and S. Quay, “Simultaneous Driver Sizing and Buffer Insertion Using a Delay Penalty Estimation Technique,” Proc. Int'l Symp. Physical Design, pp. 104-109, 2002.
[16] C. Albrecht, A.B. Kahng, I. Mandoiu, and A. Zelikovsky, “Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment, and Buffer/Wire Sizing,” Proc. Int'l Conf. VLSI Design, pp. 580-587, 2002.
[17] M. Hashimoto, M. Takahashi, and H. Onodera, “Crosstalk Noise Optimization by PostLayout Transistor Sizing,” Proc. Int'l Symp. Physical Design (ISPD), pp. 126-130, 2002.
[18] D. Sinha and H. Zhou, “Gate Sizing for Crosstalk Reduction under Timing Constraints by Lagrangian Relaxation,” Proc. Int'l Conf. Computer Aided Design (ICCAD), pp. 14-19, 2004.
[19] A. Murugavel and N. Ranganathan, “Gate Sizing and Buffer Insertion Using Economic Models for Power Optimization,” Proc. Int'l Conf. VLSI Design, pp. 195-200, 2004.
[20] C. Papadimitriou, “Algorithms, Games, and the Internet,” Proc. ACM Symp. Theory of Computing, pp. 749-753, 2001.
[21] F. Forgo, J. Szep, and F. Szidarovszky, Non-Convex Optimization and Its Applications: Introduction to the Theory of Games—Concepts, Methods, Applications. Kluwer Academic, 1999.
[22] A. Vetta, “Nash Equilibria in Competitive Societies, with Applications to Facility Location, Traffic Routing and Auctions,” Proc. IEEE Symp. Foundations of Computational Science, pp. 416-425, Nov. 2002.
[23] E. Rasmusen, Games and Information: An Introduction to Game Theory, third ed. Blackwell Publishers, 2001.
[24] J. von Neumann, “Zur Theorie der Gesellschaftsspiele,” Zur Theorie der Gesellschaftsspiele, pp. 295-320, 1928.
[25] J.F. Nash, “The Bargaining Problem,” Econometrica, vol. 18, no. 2, pp. 155-162, Apr. 1950.
[26] T. Roughgarden, “Stackelberg Scheduling Strategies,” Proc. ACM, pp. 104-113, 2001.
[27] J.F. Nash, “Equilibrium Points in N-Person Games,” Proc. Nat'l Academy of Science of the United States of Am., vol. 36, no. 1, pp. 48-49, Jan. 1950.
[28] T.-C. Chen, S.-R. Pan, and Y.-W. Chang, “Timing Modeling and Optimization under the Transmission Line Model,” IEEE Trans. VLSI Systems, vol. 12, no. 1, pp. 28-41, Jan. 2004.
[29] S. Seki and H. Hasegawa, “Analysis of Crosstalk in Very High-Speed LSI/VLSIs Using a Coupled Multi-Conductor Stripline Model,” IEEE Trans. Microwave Theory Technology, vol. 32, pp.1715-1720, Dec. 1984.
[30] D. Sylvester and C. Hu, “Analytical Modeling and Characterization of Deep Submicrometer Interconnect,” Proc. IEEE, vol. 89, no. 5, pp. 634-664, May 2001.
[31] C.S. Walker, Capacitance, Inductance, and Crosstalk Analysis. Boston: Artech House, 1990.
[32] Open Cores, “Free Open Source IP Cores and Chip Design,” http:/www.opencores.org, 2006.
[33] GALib, “Galib—A C++ Library of Genetic Algorithm Components,” http://lancet.mit.eduga/, 2006.
[34] LANCELOT, “A Package for Large-Scale Nonlinear Optimization,” http://www.numerical.rl.ac.uk/lancelotblurb.html , 2006.
[35] S. Kakutani, “A Generalization of Brouwer's Fixed Point Theorem,” Duke J. Math., vol. 8, pp. 457-459, 1941.

Index Terms:
Game theory, gate sizing, crosstalk noise, interconnect delay, interconnect models, transmission lines.
Citation:
Narender Hanchate, Nagarajan Ranganathan, "Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory," IEEE Transactions on Computers, vol. 55, no. 8, pp. 1011-1023, Aug. 2006, doi:10.1109/TC.2006.131
Usage of this product signifies your acceptance of the Terms of Use.