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Optimizing the Length of Checking Sequences
May 2006 (vol. 55 no. 5)
pp. 618-629
Hasan Ural, IEEE Computer Society
A checking sequence, generated from a finite state machine, is a test sequence that is guaranteed to lead to a failure if the system under test is faulty and has no more states than the specification. The problem of generating a checking sequence for a finite state machine M is simplified if M has a distinguishing sequence: an input sequence \bar{D} with the property that the output sequence produced by M in response to \bar{D} is different for the different states of M. Previous work has shown that, where a distinguishing sequence is known, an efficient checking sequence can be produced from the elements of a set A of sequences that verify the distinguishing sequence used and the elements of a set \Upsilon of subsequences that test the individual transitions by following each transition t by the distinguishing sequence that verifies the final state of t. In this previous work, A is a predefined set and \Upsilon is defined in terms of A. The checking sequence is produced by connecting the elements of \Upsilon and A to form a single sequence, using a predefined acyclic set E_c of transitions. An optimization algorithm is used in order to produce the shortest such checking sequence that can be generated on the basis of the given A and E_c. However, this previous work did not state how the sets A and E_c should be chosen. This paper investigates the problem of finding appropriate A and E_c to be used in checking sequence generation. We show how a set A may be chosen so that it minimizes the sum of the lengths of the sequences to be combined. Further, we show that the optimization step, in the checking sequence generation algorithm, may be adapted so that it generates the optimal E_c. Experiments are used to evaluate the proposed method.

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Index Terms:
Finite state machine, checking sequence, test minimization, distinguishing sequence.
Rob M. Hierons, Hasan Ural, "Optimizing the Length of Checking Sequences," IEEE Transactions on Computers, vol. 55, no. 5, pp. 618-629, May 2006, doi:10.1109/TC.2006.80
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