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A DRAM/SRAM Memory Scheme for Fast Packet Buffers
May 2006 (vol. 55 no. 5)
pp. 588-602
We address the design of high-speed packet buffers for Internet routers. We use a general DRAM/SRAM architecture for which previous proposals can be seen as particular cases. For this architecture, large SRAMs are needed to sustain high line rates and a large number of interfaces. A novel algorithm for DRAM bank allocation is presented that reduces the SRAM size requirements of previously proposed schemes by almost an order of magnitude, without having memory fragmentation problems. A technological evaluation shows that our design can support thousands of queues for line rates up to 160 Gbps.

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Index Terms:
Router architecture, packet buffers, high-performance memory systems, storage schemes.
Citation:
Jorge Garc?a-Vidal, Maribel March, Lloren? Cerd?, Jes? Corbal, Mateo Valero, "A DRAM/SRAM Memory Scheme for Fast Packet Buffers," IEEE Transactions on Computers, vol. 55, no. 5, pp. 588-602, May 2006, doi:10.1109/TC.2006.63
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