This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders
May 2006 (vol. 55 no. 5)
pp. 534-540
In this paper, a methodology for the development of fault-tolerant adders based on the Radix 2 Signed Digit (SD) representation is presented. The use of a number representation characterized by a carry propagation confined to neighbor digits implies interesting advantages in terms of error detection, fault localization, and repair. Errors caused by faults belonging to a considered stuck-at fault set can be detected by a parity-based technique. In fact, a carry-free adder preserving the parity of the augends can be implemented allowing fault detection by using a parity checker. Regarding fault localization, the "carry-free” property of the adder ensures the confinement of the error due to a permanent fault to only few digits. The detection of the faulty digit has been obtained by using a recomputation with shifted operands method. Finally, after the fault localization, graceful degradation of the system intended as the reduction of the performances versus a correct output computation can be obtained by using two different procedures. The first one allows obtaining the correct output by recomputing the result performing two different shift operations and using the intersection of the obtained results to recover the correct output, while the second one is based on a reduced dynamic range approach, which allows us to obtain the result in only one step, but with fewer output digits.

[1] J.F. Ziegler, “Electronic Reliability— Effects of Terrestrial Cosmic Rays,” special report to NASA, Nov. 2000 (unpublished).
[2] J. Fabula, A. Lesea, and J. Moore, “Neutron-Induced Soft Error Sensitivity Characterization of FPGAs,” Xilinx FPGA White Paper, Nov. 2004.
[3] W.W. Peterson, “On Checking an Adder,” IBM J. Research and Development, vol. 2, pp. 166-168, Apr. 1958.
[4] D. Nikolos, A.M. Paschalis, and G. Philokyprou, “Efficient Design of Totally Self-Checking Checkers for All Low-Cost Arithmetic Codes,” IEEE Trans. Computers, vol. 37, no. 7, pp. 807-814, July 1988.
[5] F.F. Sellers, M.-Y Hsiao, and L.W. Bearnson, Error Detecting Logic for Digital Computers. McGraw-Hill, 1968.
[6] O.N. Garcia and T.R.N. Rao, “On the Method of Checking Logical Operations,” Proc. Second Ann. Princeton Conf. Information Science System, pp. 89-95, 1968.
[7] M. Nicolaidis, “Carry Checking/Parity Prediction Adders and ALUs,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 11, no. 1, pp. 121-128, Feb. 2003.
[8] J.-C. Lo, S. Thanawastien, T.R.N. Rao, and M. Nicolaidis, “An SFS Berger Check Prediction ALU and Its Application to Self-Checking Processors Designs,” IEEE Trans. Computer-Aided Design, pp. 525-540, Mar. 1992.
[9] J.H. Patel and L.Y. Fung, “Concurrent Error Detection in ALU's by Recomputing with Shifted Operands,” IEEE Trans. Computers, vol. 31, no. 7, pp. 589-95, July 1982.
[10] J. Li and E. Swartzlander, “Concurrent Error Detection in ALUs by Recomputing with Rotated Operands,” Proc. IEEE Int'l Workshop Defect and Fault Tolerance in VLSI Systems, pp. 109-116, Nov. 1992.
[11] M. Alderighi, S. D'Angelo, C. Metra, and G.R. Sechi, “Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs,” Proc. IEEE Int'l Symp. Defect and Fault Tolerance in VLSI Systems, pp. 155-163, Oct. 2000.
[12] M.A. Thornton, “Signed Binary Addition Circuitry with Inherent Even Parity Outputs,” IEEE Trans. Computers, vol. 46, no. 7, pp. 811-816, July 1997.
[13] W.J. Townsend, M.A. Thornton, and P.K. Lala, “On-Line Error Detection in a Carry-Free Adder,” Proc. 11th IEEE/ACM Int'l Workshop Logic & Synthesis, pp. 251-254, June 2002.
[14] L.-L. Yang, L. Hanzo, “Redundant Residue Number System Based Error Correction Codes,” Proc. Vehicular Technology Conf., vol. 3, pp. 1472-1476, Oct. 2001.
[15] H. Krishna, K.-Y. Lin, and J.-D. Sun, “A Coding Theory Approach to Error Control in Redundant Residue Number Systems. I. Theory and Single Error Correction,” IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 39, no. 1, pp. 8-17, Jan. 1992.
[16] G.C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, and A. Salsano, “Error Detection in Signed Digit Arithmetic Circuit with Parity Checker,” Proc. 18th IEEE Int'l Symp. Defect and Fault Tolerance in VLSI Systems, pp. 401-408, Nov. 2003.
[17] I. Koren, Computer Arithmetic Algorithms. Prentice Hall, 1993.
[18] M. Ercegovac and T. Lang, Digital Arithmetic. Morgan Kaufman, 2004.
[19] A. Avizienis, “Signed-Digit Number Representations for Fast Parallel Arithmetic,” IRE Trans. Electronic Computers, vol. 10, pp. 389-400, 1961.
[20] N. Takagi, H. Yasuura, and S. Yajima, “High Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree,” IEEE Trans. Computers, vol. 34, no. 9, pp. 789-796, Sept 1985.
[21] http:/www.synopsys.com/, 2006.
[22] http:/www.erc.msstate.edu/, 2006.
[23] C. Bolchini, F. Salice, and D. Sciuto, “Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks,” Proc. Seventh Great Lakes Symp. VLSI, pp. 32-37, Mar. 1997.
[24] N.A. Touba and E.J. McCluskey, “Logic Synthesis of Multilevel Circuits with Concurrent Error Detection,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 7, pp. 783-789, July 1997.
[25] R. Brent and H.T. Kung, “A Regular Layout for Parallel Adders,” IEEE Trans. Computers, vol. 31, no. 3, pp. 260-264, Mar. 1982.

Index Terms:
Fault tolerance, high-speed arithmetic, error checking.
Citation:
Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano, "Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders," IEEE Transactions on Computers, vol. 55, no. 5, pp. 534-540, May 2006, doi:10.1109/TC.2006.76
Usage of this product signifies your acceptance of the Terms of Use.