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DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
April 2006 (vol. 55 no. 4)
pp. 470-485
Existing approaches for modular manufacturing test of core-based system-on-a-chip (SOC) devices do not provide any explicit mechanism for delivering two-pattern tests in the broadside mode, which is necessary to achieve reliable coverage of delay and stuck-open faults. Although wrapper input cells can be enhanced with two memory elements to address this problem, this will incur a large test area overhead. This paper proposes a novel architecture for broadside two-pattern test of core-based SOCs without any loss in fault coverage and without increasing the size of the wrapper input cells. The proposed solution combines the dedicated bus-based test access mechanism and functional interconnects for test data transfer in order to provide full controllability of the wrapper input cells in the two consecutive clock cycles required by two-pattern testing. New algorithms for test access mechanism design and test scheduling are proposed and design trade-offs between test area and testing time are discussed using experimental results.

[1] J. Aerts and E.J. Marinissen, “Scan Chain Design for Test Time Reduction in Core-Based ICs,” Proc. IEEE Int'l Test Conf. (ITC), pp. 448-457, Oct. 1998.
[2] K. Arabi, H. Ihs, C. Dufaza, and B. Kaminska, “Digital Oscillation-Test Method for Delay and Stuck-At Fault Testing of Digital Circuits,” Proc. IEEE Int'l Test Conf. (ITC), pp. 91-100, 1998.
[3] F. Brglez, D. Bryan, and K. Kozminski, “Combinational Profiles of Sequential Benchmark Circuits,” Proc. Int'l Symp. Circuits and Systems (ISCAS), pp. 1929-1934, 1989.
[4] M. Bushnell and V. Agrawal, Essentials of Electronic Testing. Kluwer Academic, 2000.
[5] K. Chakrabarty, R. Mukherjee, and A.S. Exnicios, “Synthesis of Transparent Circuits for Hierarchical and System-on-a-Chip Test,” Proc. IEEE Int'l Conf. VLSI Design (ICVD), pp. 431-436, Jan. 2001.
[6] P. Franco, S. Ma, J. Chang, C. Yi-Chin, S. Wattal, E. McCluskey, R. Strokes, and W. Farwell, “Analysis and Detection of Timing Failures in an Experimental Test Chip,” Proc. IEEE Int'l Test Conf. (ITC), pp. 691-700, 1996.
[7] J. Gatej, S. Lee, C. Pyron, and R. Raina, “Evaluating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits,” Proc. IEEE Int'l Test Conf. (ITC), pp. 1040-1049, Oct. 2002.
[8] I. Ghosh, S. Dey, and N.K. Jha, “A Fast and Low-Cost Testing Technique for Core-Based System-Chips,” IEEE Trans. Computer-Aided Design, vol. 19, no. 8, p. 863, Aug. 2000.
[9] S.K. Goel and E.J. Marinissen, “Effective and Efficient Test Architecture Design for SOCs,” Proc. IEEE Int'l Test Conf. (ITC), pp. 529-538, Oct. 2002.
[10] S.K. Goel and E.J. Marinissen, “Control-Aware Test Architecture Design for Modular SOC Testing,” Proc. IEEE European Test Workshop (ETW), pp. 57-62, May 2003.
[11] S.K. Goel and E.J. Marinissen, “Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization,” Proc. Design, Automation, and Test in Europe (DATE), pp. 738-743, Mar. 2003.
[12] I. Hamzaoglu and J.H. Patel, “Compact Two-Pattern Test Set Generation for Combinational and Full Scan Circuits,” Proc. IEEE Int'l Test Conf. (ITC), pp. 944-953, 1998.
[13] Y. Huang, W.-T. Cheng, C.-C. Tsai, N. Mukherjee, O. Samman, Y. Zaidan, and S.M. Reddy, “Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SOC Design,” Proc. IEEE Asian Test Symp. (ATS), pp. 265-270, Nov. 2001.
[14] IEEE Std 1500, IEEE Standard for Embedded Core Test— IEEE Std. 1500-2004. New York: IEEE, 2004.
[15] V. Immaneni and S. Raman, “Direct Access Test Scheme— Design of Block and Core Cells for Embedded ASICs,” Proc. IEEE Int'l Test Conf. (ITC), pp. 488-492, Sept. 1990.
[16] V. Iyengar and K. Chakrabarty, “Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip,” Proc. IEEE VLSI Test Symp. (VTS), pp. 368-374, May 2001.
[17] V. Iyengar, K. Chakrabarty, and E.J. Marinissen, “Co-Optimization of Test Wrapper and Test Access Architecture for Embedded Cores,” J. Electronic Testing: Theory and Applications, vol. 18, no. 2, pp. 213-230, Apr. 2002.
[18] V. Iyengar, K. Chakrabarty, and E.J. Marinissen, “Efficient Wrapper/TAM Co-Optimization for Large SOCs,” Proc. Design, Automation, and Test in Europe (DATE), pp. 491-498, Mar. 2002.
[19] V. Iyengar, K. Chakrabarty, and E.J. Marinissen, “Integrated Wrapper/TAM Co-Optimization, Constraint-Driven Test Scheduling, and Tester Data Volume Reduction for SOCs,” Proc. ACM/IEEE Design Automation Conf. (DAC), pp. 685-690, June 2002.
[20] V. Iyengar, K. Chakrabarty, and E.J. Marinissen, “On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization,” Proc. IEEE VLSI Test Symp. (VTS), pp. 253-258, Apr. 2002.
[21] V. Iyengar, S.K. Goel, K. Chakrabarty, and E.J. Marinissen, “Test Resource Optimization for Multi-Site Testing of SOCs under ATE Memory Depth Constraints,” Proc. IEEE Int'l Test Conf. (ITC), pp. 1159-1168, Oct. 2002.
[22] R. Kapur and T.W. Williams, “Manufacturing Test of SoCs,” Proc. IEEE Asian Test Symp. (ATS), pp. 317-319, Nov. 2002.
[23] S. Koranne, “Formulating SoC Test Scheduling as a Network Transportation Problem,” IEEE Trans. Computer-Aided Design, vol. 21, no. 12, pp. 1517-1525, Dec. 2002.
[24] X. Lin, R. Press, J. Rajski, P. Reuter, T. Rinderknecht, B. Swanson, and N. Tamarapalli, “High-Frequency, At-Speed Scan Testing,” IEEE Design and Test of Computers, vol. 20, no. 5, pp. 17-25, Oct. 2003.
[25] R. Madge, B.R. Benware, and W.R. Daasch, “Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs,” IEEE Design and Test of Computers, vol. 20, no. 5, pp. 46-53, Oct. 2003.
[26] E.J. Marinissen, R. Arendsen, G. Bos, H. Dingemanse, M. Lousberg, and C. Wouters, “A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores,” Proc. IEEE Int'l Test Conf. (ITC), pp. 284-293, Oct. 1998.
[27] E.J. Marinissen, S.K. Goel, and M. Lousberg, “Wrapper Design for Embedded Core Test,” Proc. IEEE Int'l Test Conf. (ITC), pp. 911-920, Oct. 2000.
[28] E.J. Marinissen, V. Iyengar, and K. Chakrabarty, “ITC'02 SOC Test Benchmarks Web Site,” http://www.hitech-projects.comitc02 socbenchm /, 2006.
[29] E.J. Marinissen, R. Kapur, M. Lousberg, T. Mclaurin, M. Ricchetti, and Y. Zorian, “On IEEE P1500's Standard for Embedded Core Test,” J. Electronic Testing: Theory and Applications, vol. 18, nos. 4/5, pp. 365-383, Aug. 2002.
[30] P. Maxwell, R. Aitken, K. Kollitz, and A. Brown, “IDDQ and AC Scan: The War against Unmodelled Defects,” Proc. IEEE Int'l Test Conf. (ITC), pp. 250-258, 1996.
[31] M. Nourani and C. Papachristou, “Structural Fault Testing of Embedded Cores Using Pipelining,” J. Electronic Testing: Theory and Applications, vol. 15, no. 1, p. 129, 1999.
[32] S. Pateras, “Achieving At-Speed Stuctural Test,” IEEE Design and Test of Computers, vol. 20, no. 5, pp. 26-33, Oct. 2003.
[33] J. Rearick, “Too Much Delay Fault Coverage Is a Bad Thing,” Proc. IEEE Int'l Test Conf. (ITC), pp. 624-633, Nov. 2001.
[34] R.L. Wadsack, “Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits,” Bell Systems Technical J., pp. 1449-1474, May-June 1978.
[35] N. Touba and B. Pouya, “Using Partial Isolation Rings to Test Core-Based Designs,” IEEE Design and Test of Computers, vol. 14, no. 4, pp. 52-59, Dec. 1997.
[36] P. Varma, “On Path Delay Testing in a Standard Scan Environment,” Proc. IEEE Int'l Test Conf. (ITC), pp. 164-173, Oct. 1994.
[37] P. Varma and S. Bhatia, “A Structured Test Re-Use Methodology for Core-Based System Chips,” Proc. IEEE Int'l Test Conf. (ITC), pp. 294-302, Oct. 1998.
[38] H. Vermaak and H. Kerkhoff, “Enhanced P1500 Compliant Wrapper suitable for Delay Fault Testing of Embedded Cores,” Proc. IEEE European Test Workshop (ETW), pp. 121-126, May 2003.
[39] L. Whetsel, “An IEEE 1149. 1 Based Test Access Architecture for ICs with Embedded Cores,” Proc. IEEE Int'l Test Conf. (ITC), pp. 69-78, Nov. 1997.
[40] Q. Xu, “Updated ITC'02 Benchmark SOCs with Random Functional Interconnect Information,” http://www.ece.mcmaster.ca/~nicolacadt.html , 2006.
[41] Q. Xu and N. Nicolici, “Resource-Constrained System-on-a-Chip Test: A Survey,” IEE Proc. Computers and Digital Techniques, vol. 152, no. 1, pp. 67-81, Jan. 2005.
[42] T. Yoneda and H. Fujiwara, “Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores,” J. Electronic Testing: Theory and Applications, vol. 18, nos. 4/5, pp. 487-501, Aug. 2002.
[43] Y. Zorian, E.J. Marinissen, and S. Dey, “Testing Embedded-Core-Based System Chips,” Computer, vol. 32, no. 6, pp. 52-60, June 1999.
[44] W. Zou, S.M. Reddy, I. Pomeranz, and Y. Huang, “SOC Test Scheduling Using Simulated Annealing,” Proc. IEEE VLSI Test Symp. (VTS), pp. 325-330, Apr. 2003.

Index Terms:
System-on-a-chip, embedded core delay test.
Citation:
Qiang Xu, Nicola Nicolici, "DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs," IEEE Transactions on Computers, vol. 55, no. 4, pp. 470-485, April 2006, doi:10.1109/TC.2006.56
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