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Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes
April 2006 (vol. 55 no. 4)
pp. 373-384
We consider the optimal design problem for arbitrary-shaped switch box, (r_1, \ldots, r_k){\hbox{-}}{\rm SB}, in which r_i terminals are located on side i for i = 1, \ldots, k and programmable switches are joining pairs of terminals from different sides. Previous investigations on switch box designs mainly focused on regular switch boxes in which all sides have the same number of terminals. By allowing different numbers of terminals on different sides, irregular switch boxes are more general and flexible for applications such as customized FPGAs and reconfigurable interconnection networks. The optimal switch box design problem is to design a switch box satisfying the given shape and routing capacity specifications with the minimum number of switches. We present a decomposition design method for a wide range of irregular switch boxes. The main idea of our method is to model a routing requirement as a nonnegative integer vector satisfying a system of linear equations and then derive a decomposition theory of routing requirements based on the theory of systems of linear Diophantine equations. The decomposition theory makes it possible to construct a large irregular switch box by combining small switch boxes of fixed sizes. Specifically, we can design a family of hyperuniversal (universal) (w {\bf{d}}+{\bf{c}}){\hbox{-}}{\rm SBs} with \Theta(w) switches, where {\bf{d}} and {\bf{c}} are constant vectors and w is a scalar. We illustrate the design method by designing a class of optimal hyperuniversal irregular 3-sided switch boxes and a class of optimal rectangular universal switch boxes. Experimental results on the rectangular universal switch boxes with the VPR router show that the optimal design of irregular switch boxes does pay off.

[1] V. Betz and J. Rose, “Directional Bias and Non-Uniformity in FPGA Global Routing Architectures,” Proc. IEEE/ACM Int'l Conf. Computer-Aided Design, pp. 652-659, 1996.
[2] V. Betz and J. Rose, “A New Packing, Placement and Routing Tool for FPGA Research,” Proc. Seventh Int'l Workshop Field-Programmable Logic and Applications, pp. 213-222, 1997.
[3] V. Betz, J. Rose, and A. Marquardt, Architecure and CAD for Deep-Submicron FPGAs. Boston: Kluwer Academic, 1999.
[4] S. Brown, R. Francis, J. Rose, and Z. Vranesic, Field Programmable Gate Arrays. Boston: Kluwer-Academic, 1992.
[5] Y.-W. Chang, D.F. Wong, and C.K. Wong, “Universal Switch Modules for FPGA Design,” ACM Trans. Design Automation of Electronic Systems, vol. 1, no. 1, pp. 80-101, Jan. 1996.
[6] E. Contejean and H. Devie, “An Efficient Incremental Algorithm for Solving Systems of Linear Diophantine Equations,” Information and Computing, vol. 113, no. 1, pp. 143-172, 1994.
[7] A. DeHon, “Balancing Interconnect and Computation in a Reconfigurable Computing Array,” Proc. ACM/SIGDA Seventh Int'l Symp. Field Programmable Gate Arrays, pp. 69-78, 1999.
[8] H. Fan, J. Liu, Y. Wu, and C.C. Cheung, “On Optimum Switch Box Designs for 2-D FPGAs,” Proc. Design Automation Conf. (DAC-01), pp. 203-208, 2001.
[9] H. Fan, J. Liu, Y. Wu, and C.C. Cheung, “On Optimal Hyper Universal and Rearrageable Switch Box Designs,” IEEE Trans. Computer Aided Designs, vol. 22, no. 12, pp. 1637-1649, Dec. 2003.
[10] H. Fan, J. Liu, Y. Wu, and C. Wong, “Reduction Design for Generic Universal Switch Blocks,” ACM Trans. Design Automation of Electronic Systems, vol. 7, no. 4, pp. 526-546, Oct. 2002.
[11] H. Fan, J. Liu, and Y.L. Wu, “General Models and a Reduction Design Technique for FPGA Switch Box Designs,” IEEE Trans. Computers, vol. 52, no. 1, pp. 21-30, Jan. 2003.
[12] P. Hallschmid and S. Wilton, “Detailed Routing Architectures for Embedded Programmable Logic IP Cores,” Proc. ACM/SIGDA Int'l Symp. Field-Programmable Gate Arrays, pp. 69-74, Feb. 2001.
[13] J. Rose and S. Brown, “Flexibility of Interconnection Structures for Field-Programmable Gate Arrays,” IEEE J. Solid State Circuits, vol. 26, no. 3, pp. 277-282, Mar. 1991.
[14] M. Shyu, G.M. Wu, Y.D. Chang, and Y.W. Chang, “Generic Universal Switch Blocks,” IEEE Trans. Computers, vol. 49, no. 4, pp. 348-359, Apr. 2000.
[15] M. Yen, S. Chen, and S. Lan, “A Three-Stage One-Sided Rearrangeable Polygonal Switching Network,” IEEE Trans. Computers, vol. 50, no. 11, pp. 1291-1294, Nov. 2001.

Index Terms:
FPGA, reconfigurable interconnection network, switch box, switch block, universal, hyperuniversal.
Citation:
Hongbing Fan, Yu-Liang Wu, Ray Chak-Chung Cheung, Jiping Liu, "Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes," IEEE Transactions on Computers, vol. 55, no. 4, pp. 373-384, April 2006, doi:10.1109/TC.2006.55
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