This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Diversity Analysis in the Presence of Delay Faults Affecting Duplex Systems
March 2006 (vol. 55 no. 3)
pp. 348-352
This paper analyzes the problem of timing related common mode failures in redundant systems. The specific case of duplex systems in the presence of delay faults is analyzed by providing a probabilistic characterization of undetectable errors. PDF simulation was used to evaluate the probability of undetectable errors in conventional duplex systems and in duplex systems making use of a simple kind of data diversity.

[1] J. Lala and R. Harper, “Architectural Properties for Safety Critical Real-Time Applications,” Proc. IEEE, vol. 82, no. 1, pp. 25-40, 1994.
[2] S. Mitra, N. Saxena, and E. McCluskey, “Common Mode Failures in Redundant VLSI Systems: A Survey,” IEEE Trans. Reliability, vol. 49, no. 3, pp. 285-295, 2000.
[3] A. Avizienis and J. Kelly, “Fault Tolerance by Design Diversity, Concepts and Experiments,” Computer, pp. 67-80, Aug. 1984.
[4] S. Mitra and E. McCluskey, “Combinational Logic Synthesis for Diversity in Duplex Systems,” Proc. IEEE Int'l Test Conf., pp. 179-188, 2000.
[5] S. Mitra, N. Saxena, and E. McCluskey, “A Design Diversity Metric and Analysis of Redundant Systems,” IEEE Trans. Computers, vol. 51, no. 5, pp. 498-510, May 2002.
[6] M. Sivaraman and A. Strojwas, A Unified Approach for Timing Verification and Delay Fault Testing. Kluwer-A.P., 1998.
[7] M. Alderighi, S. D'Angelo, C. Metra, and G. Sechi, “Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs,” Proc. IEEE Int'l Symp. Defect and Fault Tolerance in VLSI Systems, pp. 155-163, 2000.
[8] J. Patel and L. Fung, “Multiplier and Divider Arrays with Concurrent Error Detection,” Proc. Int'l Symp. Fault-Tolerant Computing, p. 268, 1995.
[9] E. Park and M. Mercer, “Robust and Nonrobust Tests for Path Delay Faults in a Combinational Circuit,” Proc. IEEE Int'l Test Conf., pp. 1027-1034, 1987.
[10] F. Brglez and H. Fujiwara, “A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran,” Proc. IEEE Int'l Symp. Circuit and Systems, pp. 663-698, 1985.
[11] P. Nigh, “The Importance of On-Line Testing to Enhance High-Reliability Performance,” Proc. IEEE Int'l Test Conf., p. 1281, 2003.
[12] W. Mao and M. Ciletti, “A Quantitative Measure of Robustness for Delay Fault Testing,” Proc. European Design Automation Conf. (Euro-DAC), pp. 543-549, 1992.
[13] K.-T. Cheng, A. Krstic, and H.-C. Chen, “Generation of High Quality Tests for Robustly Untestable Path Delay Faults Coverage of Path Delay Faults,” IEEE Trans. Computers, vol. 45, no. 12, pp. 1379-1392, Dec. 1996.
[14] K. Bowman, S. Duvall, and J. Meindl, “Impact of Die-to-Die and Within-Die Parameter Fluctuations for the Maximum Clock Frequency Distribution for Gigascale Integration,” IEEE J. Solid State Circuits, vol. 37, no. 2, pp. 183-190, 2002.
[15] Y.-S. Chang, S.K. Gupta, and M. Breuer, “Test Generation for Ground Bounce in Internal Logic Circuitry,” Proc. IEEE VLSI Test Symp., pp. 110-116, 1997.

Index Terms:
Online error detection, duplex systems, timing related failures.
Citation:
Michele Favalli, "Diversity Analysis in the Presence of Delay Faults Affecting Duplex Systems," IEEE Transactions on Computers, vol. 55, no. 3, pp. 348-352, March 2006, doi:10.1109/TC.2006.37
Usage of this product signifies your acceptance of the Terms of Use.