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Double-Residue Modular Range Reduction for Floating-Point Hardware Implementations
March 2006 (vol. 55 no. 3)
pp. 254-267
In this paper, we present a novel algorithm and the corresponding architecture for performing range reduction, which is a preprocessing task required for the evaluation of some elementary functions such as trigonometric and exponential-based functions. The proposed algorithm introduces a modification to the Modular Range Reduction algorithm which increases the speed of computation and allows us to design an architecture for the floating-point case. The implementation presented admits as an input argument any representable number of the standard single precision IEEE 754 floating-point representation and provides the maximum accuracy to the final result. This supposes a hardware solution to the problem of having an input argument close to a multiple of the constant. A final comparison with other implementations is presented.

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Index Terms:
Range-reduction, elementary function evaluation, floating-point arithmetic.
Citation:
Julio Villalba, Tomas Lang, Mario A. Gonzalez, "Double-Residue Modular Range Reduction for Floating-Point Hardware Implementations," IEEE Transactions on Computers, vol. 55, no. 3, pp. 254-267, March 2006, doi:10.1109/TC.2006.38
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