This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency
February 2006 (vol. 55 no. 2)
pp. 199-213
ASCII Text
x 
 
Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose, "Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency," IEEE Transactions on Computers, vol. 55, no. 2, pp. 199-213, February, 2006.
 
 
BibTex
x
 
@article{ 10.1109/TC.2006.23,
author = {Dmitry Ponomarev and Gurhan Kucuk and Kanad Ghose},
title = {Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency},
journal ={IEEE Transactions on Computers},
volume = {55},
number = {2},
issn = {0018-9340},
year = {2006},
pages = {199-213},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2006.23},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency
IS - 2
SN - 0018-9340
SP199
EP213
EPD - 199-213
A1 - Dmitry Ponomarev,
A1 - Gurhan Kucuk,
A1 - Kanad Ghose,
PY - 2006
KW - Index Terms- Superscalar processor
KW - energy-efficient datapath
KW - power reduction
KW - dynamic instruction scheduling.
VL - 55
JA - IEEE Transactions on Computers
ER -
 
The "one-size-fits-all” philosophy used for permanently allocating datapath resources in today's superscalar CPUs to maximize performance across a wide range of applications results in the overcommitment of resources in general. To reduce power dissipation in the datapath, the resource allocations can be dynamically adjusted based on the demands of applications. We propose a mechanism to dynamically, simultaneously, and independently adjust the sizes of the issue queue (IQ), the reorder buffer (ROB), and the load/store queue (LSQ) based on the periodic sampling of their occupancies to achieve significant power savings with minimal impact on performance. Resource upsizing is done more aggressively (compared to downsizing), using the relative rate of blocked dispatches to limit the performance penalty. Our results are validated by the execution of the SPEC 2000 benchmark suite on a substantially modified version of the Simplescalar simulator, where the IQ, the ROB, the LSQ, and the register files are implemented as separate structures, as is the case with most practical implementations. We also use actual VLSI layouts of the datapath components in a 0.18 micron process to accurately measure the energy dissipations for each type of access. For a 4-way superscalar CPU, an average power savings of about 42 percent within the IQ, 74 percent within the ROB (integrating the register file), and 41 percent within the LSQ can be achieved with an average performance penalty of about 5 percent.

[1] , Advanced Configuration and Power Interface Specification (Intel, Microsoft, Toshiba), 1999.
[2] D. Albonesi, “Selective Cache ways: On-Demand Cache Resource Allocation,” Proc. Int'l Symp. Microarchitecture, 1999.
[3] D. Brooks, V. Tiwari, and M. Martonosi, “Wattch: A Framework for Architectural-Level Power Analysis and Optimizations,” Proc. 27th Int'l Symp. Computer Architecture, 2000.
[4] D. Brooks and M. Martonosi, “Dynamic Thermal Management for High-Performance Microprocessors,” Proc. Seventh Int'l Symp. High-Performance Computer Architecture, 2001.
[5] I. Bahar and S. Manne, “Power and Energy Reduction via Pipeline Balancing,” Proc. Int'l Symp. Computer Architecture, pp. 218-229, 2001.
[6] R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas, “Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures,” Proc. 34th Int'l Symp. Microarchitecture, 2000.
[7] D. Bhandarkar, Alpha Implementations and Architecture Complete Reference and Guide. Digital Press, 1996.
[8] D. Burger and T.M. Austin, “The SimpleScalar Tool Set: Version 2.0,” technical report, Dept. of Computer Science, Univ. of Wisconsin-Madison, June 1997, and documentation for all SimpleScalar releases.
[9] A. Buyuktosunoglu, D. Albonesi, S. Schuster, D. Brooks, P. Bose, and P. Cook, “A Circuit Level Implementation of an Adaptive Issue Queue for Power-Aware Microprocessors,” Proc. Great Lakes Symp. VLSI Design, 2001.
[10] A. Buyuktosunoglu, S. Schuster, D. Brooks, P. Bose, P. Cook, and D. Albonesi, “An Adaptive Issue Queue for Reduced Power at High Performance,” Proc. Workshop Power-Aware Computer Systems, Nov. 2000.
[11] G. Cai, “Architectural Level Power/Performance Optimization and Dynamic Power Estimation,” Proc. Cool-Chips Tutorial: An Industrial Perspective on Low Power Processor Design, 1999.
[12] S. Dropsho et al., “Integrating Adaptive On-Chip Structures for Reduced Dynamic Power,” Proc. Int'l Conf. Parallel Architectures and Compilation Techniques (PACT), 2002.
[13] D. Folegnani and A. Gonzalez, “Energy-Effective Issue Logic,” Proc. Int'l Symp. Computer Architecture, pp. 230-239, 2001.
[14] S. Ghiasi, J. Casmira, and D. Grunwald, “Using IPC Variation in Workloads with Externally Specified Rates to Reduce Power Consumption,” Proc. Workshop Complexity-Effective Design, June 2000.
[15] M. Huang, J. Renau, S.-M. Yoo, and J. Torellas, “A Framework for Dynamic Energy Efficiency and Temperature Management,” Proc. 33rd Int'l Symp. Microarchitecture, 2000.
[16] M. Huang, J. Renau, and J. Torrellas, “Positional Adaptation of Processors: Application to Energy Reduction,” Proc. 30th Int'l Symp. Computer Architecture (ISCA), 2003.
[17] A. Iyer and D. Marculescu, “Run-Time Scaling of Microarchitecture Resources in a Processor for Energy Savings,” Proc. Kool Chips Workshop, Dec. 2000.
[18] S. Kaxiras, Z. Hu, and M. Martonosi, “Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power,” Proc. Int'l Symp. Computer Architecture, pp. 240-251, 2001.
[19] G. Kucuk, K. Ghose, D. Ponomarev, and P. Kogge, “Energy Efficient Instruction Dispatch Buffer Design for Superscalar Processors,” Proc. Int'l Symp. Low-Power Electronics and Design, pp. 237-242, 2001.
[20] Microprocessor Report, various issues, 1996-1999.
[21] S. Palacharla, N.P. Jouppi, and J.E. Smith, “Quantifying the Complexity of Superscalar Processors,” Technical report CS-TR-96-1308, Dept. of Computer Science, Univ. of Wisconsin, 1996.
[22] D. Ponomarev, G. Kucuk, and K. Ghose, “Reducing Power Requirements of Instruction Scheduling through Dynamic Allocation of Multiple Datapath Resources,” Proc. 34th Int'l Symp. Microarchitecture, pp. 90-101, 2001.
[23] D. Ponomarev, G. Kucuk, and K. Ghose, “AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors,” Proc. Fifth Design and Test in Europe Conf. (DATE '02), pp. 124-129, 2002.
[24] T. Sherwood and B. Calder, “Time Varying Behavior of Programs,” Technical Report No. CS99-630, Dept. of Computer Science and Eng., Univ. of California San Diego, Aug. 1999.
[25] D.W. Wall, “Limits on Instruction Level Parallelism,” Proc. Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS), Nov. 1991.
[26] K. Wilcox and S. Manne, “Alpha Processors: A History of Power Issues and a Look to the Future,” Cool-Chips Tutorial, Nov. 1999.
[27] V. Zyuban and P. Kogge, “Optimization of High-Performance Superscalar Architectures for Energy Efficiency,” Proc. Int'l Symp. Low-Power Electronics and Design, pp. 84-89, 2000.

Index Terms:
Index Terms- Superscalar processor, energy-efficient datapath, power reduction, dynamic instruction scheduling.
Citation:
Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose, "Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency," IEEE Transactions on Computers, vol. 55, no. 2, pp. 199-213, Feb. 2006, doi:10.1109/TC.2006.23
Usage of this product signifies your acceptance of the Terms of Use.