Issue No.02 - February (2006 vol.55)
Dmitry Ponomarev , IEEE
Kanad Ghose , IEEE
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2006.23
The "one-size-fits-all” philosophy used for permanently allocating datapath resources in today's superscalar CPUs to maximize performance across a wide range of applications results in the overcommitment of resources in general. To reduce power dissipation in the datapath, the resource allocations can be dynamically adjusted based on the demands of applications. We propose a mechanism to dynamically, simultaneously, and independently adjust the sizes of the issue queue (IQ), the reorder buffer (ROB), and the load/store queue (LSQ) based on the periodic sampling of their occupancies to achieve significant power savings with minimal impact on performance. Resource upsizing is done more aggressively (compared to downsizing), using the relative rate of blocked dispatches to limit the performance penalty. Our results are validated by the execution of the SPEC 2000 benchmark suite on a substantially modified version of the Simplescalar simulator, where the IQ, the ROB, the LSQ, and the register files are implemented as separate structures, as is the case with most practical implementations. We also use actual VLSI layouts of the datapath components in a 0.18 micron process to accurately measure the energy dissipations for each type of access. For a 4-way superscalar CPU, an average power savings of about 42 percent within the IQ, 74 percent within the ROB (integrating the register file), and 41 percent within the LSQ can be achieved with an average performance penalty of about 5 percent.
Index Terms- Superscalar processor, energy-efficient datapath, power reduction, dynamic instruction scheduling.
Dmitry Ponomarev, Kanad Ghose, "Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency", IEEE Transactions on Computers, vol.55, no. 2, pp. 199-213, February 2006, doi:10.1109/TC.2006.23